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Layered architecture for quantum computing

N. Cody Jones, Rodney Van Meter, Austin G. Fowler, Peter L. McMahon, Jungsang Kim, Thaddeus D. Ladd, Yoshihisa Yamamoto

arXiv:1010.5022v3quant-ph

TL;DR

Large-scale quantum computing requires an architecture that combines faulty physical hardware, control, error correction, and application-level operations. The paper develops a five-layer framework and a QuDOS platform based on optically controlled quantum-dot spins, then analyzes fault-tolerant resources and timing. It concludes that the studied architecture could execute factoring and quantum-simulation workloads on timescales of days, while exposing substantial overheads from error correction and ancilla distillation.

  • Problem

    Building a large-scale quantum computer requires combining hardware, control operations, error correction, and algorithmic resources rather than estimating only qubit and gate counts.

  • Method

    The paper develops a layered quantum-computer architecture alongside QuDOS, using optically controlled quantum-dot spins and surface-code fault tolerance to analyze system resources.

  • Results

    The studied quantum-dot architecture could execute fault-tolerant factoring and quantum-simulation workloads on timescales of days.

  • Takeaways & Limitations

    Layer encapsulation and resource management organize the transition from nanosecond physical operations to slower logical, error-corrected gates.

Abstract

from arXiv · show

We develop a layered quantum computer architecture, which is a systematic framework for tackling the individual challenges of developing a quantum computer while constructing a cohesive device design. We discuss many of the prominent techniques for implementing circuit-model quantum computing and introduce several new methods, with an emphasis on employing surface code quantum error correction. In doing so, we propose a new quantum computer architecture based on optical control of quantum dots. The timescales of physical hardware operations and logical, error-corrected quantum gates differ by several orders of magnitude. By dividing functionality into layers, we can design and analyze subsystems independently, demonstrating the value of our layered architectural approach. Using this concrete hardware platform, we provide resource analysis for executing fault-tolerant quantum algorithms for integer factoring and quantum simulation, finding that the quantum dot architecture we study could solve such problems on the timescale of days.

I. INTRODUCTION

The paper frames quantum computer architecture as a layered, modular approach for combining hardware, control, error correction, and application requirements. It uses this framework to organize a QuDOS design while addressing scalability challenges such as ancilla preparation, interconnection, and heterogeneous architecture.

  • Layered architecture: Quantum computer architecture combines components into layered abstractions, each grouping related functions and moving toward an ideal computing environment.The architecture decomposes complex system behavior into manageable operations and defines interfaces through services provided between layers.
  • Architectural challenges: Ancilla-state preparation is a dominant fault-tolerant subroutine, with prior ion-trap estimates assigning approximately 90% of the computer to ancilla factories.The paper examines surface-code factories and reports close agreement with that estimate.
  • Architectural challenges: Scalable architectures must address long-range coupling, data movement, heterogeneous interconnects, and the difficulty of building monolithic systems containing billions of physical qubits.Prior work spans photonic channels, teleportation, nearest-neighbor systems, cluster states, and distributed quantum-computing models.
  • Layered architecture: Layering creates modularity by allowing engineers to focus on individual challenges while preserving the system’s hierarchical organization.Interfaces can vary with the selected hardware and error-correction scheme, while the overall architecture remains organized around prescribed layer duties.
  • Layered architecture: The five-layer control stack spans the Application, Logical, Quantum Error Correction, Virtual, and Physical layers.The Physical layer hosts raw quantum processes, while intermediate layers shape them into high-accuracy fault-tolerant qubits and gates.

C. Interaction between layers

The architecture’s control cycle coordinates operations across layers while quantum processing remains confined to the Physical layer. QuDOS instantiates this framework with optically controlled electron spins in quantum dots embedded in a planar optical microcavity.

  • C. Interaction between layers: Pipelining is essential because operations in different layers occur on drastically different timescales and some control operations incur delays.The control loop must simultaneously handle layered operations and syndrome measurement for error correction.
  • C. Interaction between layers: QuDOS uses electron spins in quantum dots arranged in a two-dimensional array, with laser pulses delivered through an optical microcavity.The platform is developed alongside the layered framework as a candidate for large-scale quantum computing.
  • C. Interaction between layers: The control cycle determines operation timing and sequencing, while higher layers process and organize the Physical layer’s quantum operations.All quantum processes occur in the Physical layer, and the Application layer remains external to the hardware-dependent loop.
  • C. Interaction between layers: Physical qubits store quantum information, while higher-level control operations address imperfections and organize them into computational qubits.The host system determines the physical qubit’s immediate environment and helps characterize noise affecting operations.
  • C. Interaction between layers: The planar microcavity uses vertically stacked distributed Bragg reflector mirrors to support the two-dimensional surface-code array.Quantum dots are embedded near cavity-field antinodes to enhance interaction with the optical modes.

C. 1-qubit gate mechanism

QuDOS implements single-qubit control with magnetic-field precession and ultrafast laser pulses, while its scalable two-qubit mechanism remains the principal hardware challenge. Hadamard-pulse sequences compensate for finite pulse duration, and dispersive cavity interactions support readout and coupling proposals.

  • C. 1-qubit gate mechanism: Magnetic-field precession supplies Z-axis rotation, while laser pulses provide power-dependent rotation around an orthogonal X axis.Finite pulse duration causes simultaneous X control and Z precession, impairing direct spin manipulation.
  • C. 1-qubit gate mechanism: Two Hadamard pulses surrounding free-precession R_Z(θ) construct arbitrary X-axis rotations through R_X(θ) = H · R_Z(θ) · H.Tuning Hadamard-pulse power and duration enables high-fidelity control despite finite pulse duration.
  • C. 1-qubit gate mechanism: Scaling QuDOS to millions of parallel control operations requires MEMS mirrors and electro-optic modulators for beam steering and pulse timing.Engineering this optical imaging system is beyond the paper’s present scope.
  • D. 2-qubit gate mechanism: The practical, scalable two-qubit gate remains QuDOS’s most challenging hardware element.The paper notes that fast, all-optical control is attractive and that single- and two-qubit gates may be achievable with a single optical pulse.
  • D. 2-qubit gate mechanism: The proposed two-qubit gate uses a dispersive cavity-QED interaction whose key figure of merit is cooperativity, proportional to cavity quality factor Q divided by volume V.The design seeks enhanced cooperativity through angle-dependent response in an extended planar microcavity.
  • D. 2-qubit gate mechanism: A dispersive QND readout maps the electron-spin state onto a state-dependent optical phase shift measured by homodyne detection.The phase measurement performs projective measurement of the electron spin.

E. Measurement readout

The measurement readout layer must support fast, accurate readout compatible with fault-tolerant correction, while the Virtual layer converts physical processes into robust information primitives. QuDOS combines dynamical decoupling and controlled pulse sequences to extend coherence and construct virtual operations.

  • Measurement readout: QND measurement can be repeated, allowing classical readout noise to be reduced by time-averaging.Destructive photon-emission readout leaves the qubit in the ground state regardless of outcome and cannot be repeated.
  • Measurement readout: QuDOS proposes Faraday/Kerr rotation readout using an off-resonant probe whose phase shift depends on the electron spin state.Sensitive photodetectors and homodyne detection are part of the proposed mechanism.
  • Virtual layer: The Virtual layer converts physical effects into virtual qubits and gates, whose controlled sequences can suppress systematic errors through correlated-error cancellation.Virtual qubits may use dynamical decoupling or decoherence-free subspaces to extend their lifetime.
  • Dynamical decoupling: The 8H sequence uses eight Hadamard pulses and is selected to balance decoupling performance against execution time while correcting first-order free-evolution and control errors.For τ = 1 ns, one iteration requires 8 ns; simulations compare 8H with CP and UDD under dephasing noise and control errors.

B. Virtual gate

Virtual gates combine faulty physical control operations into sequences that suppress systematic errors through destructive interference. In QuDOS, a BB1 compensation sequence is embedded within repeated 8H dynamical-decoupling sequences, while measurement requires compatible readout handling.

  • B. Virtual gate: Virtual gates combine Layer 1 control operations so correlated control errors destructively interfere.The goal is to suppress systematic errors arising from faulty physical hardware.
  • B. Virtual gate: Compensation sequences can reduce correlated errors without requiring knowledge of their type or magnitude.Dynamically corrected gates provide an alternative by tuning the time-dependent control Hamiltonian.
  • B. Virtual gate: Accuracy evaluation of Virtual-layer operations, especially multi-qubit gates and entangled states, is beyond the paper’s present scope.The authors identify systematic evaluation as important for quantum-computer development.
  • B. Virtual gate: QuDOS embeds a BB1 compensation sequence within repeated 8H dynamical-decoupling sequences to suppress systematic environmental and control-pulse errors.The construction targets both error sources in the ultrafast physical pulses.
  • B. Virtual gate: Measurement must be coordinated with virtual control because dynamical decoupling can interfere with readout.If physical measurement is QND, repeated virtual-qubit measurements can suppress classical readout noise by majority polling.

IV. LAYER 3: QUANTUM ERROR CORRECTION

Layer 3 uses fault-tolerant quantum error correction, especially the surface code, to convert many virtual qubits into protected logical resources. Its required code distance and resource overhead depend on hardware error rates, algorithm demands, and the chosen code.

  • IV. LAYER 3: QUANTUM ERROR CORRECTION: Fault-tolerant QEC removes arbitrary errors and creates logical qubits and gates from many physical resources.Layer 2 suppresses correlated errors, whereas Layer 3 isolates and removes arbitrary errors.
  • IV. LAYER 3: QUANTUM ERROR CORRECTION: The surface code is selected for its high threshold and two-dimensional nearest-neighbor interaction geometry.The architecture remains modular enough to replace it with other QEC schemes, although the selected code affects device geometry and connectivity.
  • IV. LAYER 3: QUANTUM ERROR CORRECTION: Resources become manageable when hardware error rates are about an order of magnitude below the chosen code’s threshold.A functioning QEC system must operate below threshold, while a practical system must operate well below it.
  • IV. LAYER 3: QUANTUM ERROR CORRECTION: The required logical error rate is bounded by the algorithm’s circuit depth K and logical-qubit count Q, with εL ≪ 1/KQ.The KQ estimate assumes the worst case for a circuit of logical depth K acting on Q logical qubits.
  • IV. LAYER 3: QUANTUM ERROR CORRECTION: εV < 0.2εthresh is required; otherwise the code distance and quantum-computer size become impractically large.For 1024-bit Shor factoring, the analysis requires εL ≤ 10^-2/KQ so the algorithm’s logical error probability remains below 1%.
  • IV. LAYER 3: QUANTUM ERROR CORRECTION: 6240 virtual qubits are required for one logical qubit in a typical large-scale Shor factoring parameter set.The estimate follows from the minimum surface-code area needed to separate two lattice defects by distance d.

B. Pauli frames

Pauli frames replace many physical correction operations with classical tracking. The quantum computation proceeds normally, while final Pauli-basis measurements are interpreted using the stored frame.

  • B. Pauli frames: Because Pauli gates belong to the Clifford group, tracking them can be performed efficiently on a classical computer.The Gottesman–Knill Theorem provides the relevant efficiency guarantee.
  • B. Pauli frames: Pauli corrections are omitted from hardware and incorporated into the evolving frame.Clifford gates are implemented physically while transforming the frame according to the corresponding conjugation rule.
  • B. Pauli frames: Final measurements in the X, Y, or Z basis are modified according to the Pauli correction stored in the frame.For example, a Z frame anticommutes with an X-basis measurement and negates its interpreted result.
  • B. Pauli frames: A Pauli frame classically tracks the accumulated X, Y, Z, or I corrections for each virtual qubit.Surface-code syndrome processing identifies a likely Pauli-error pattern, and the frame records the recovery instead of applying it directly.

V. LAYER 4: LOGICAL

The Logical layer turns Layer 3’s fault-tolerant resources into a substrate capable of universal quantum computation. It supplements the code’s fundamental gates with logical Pauli frames and injected or distilled ancillas.

  • V. LAYER 4: LOGICAL: The Logical layer processes error-corrected qubits and gates to produce arbitrary gates for the Application layer.Surface-code QEC supplies only a limited gate set, so additional logical processing is required for universality.
  • V. LAYER 4: LOGICAL: Distilled |Y⟩ and |A⟩ ancillas enable surface-code implementations of S = e^(iπ/4)σZ and T = e^(iπ/8)σZ gates, respectively.These ancillas are injected into the error-correcting code and consumed in specialized circuits.
  • V. LAYER 4: LOGICAL: A logical Pauli frame transforms non-Clifford gates so the implemented operation accounts for tracked Pauli corrections.This transformation differs from the frame update produced by a Clifford gate.
  • V. LAYER 4: LOGICAL: Surface-code fundamental gates do not include the phase gate S, which the Logical layer constructs using a reusable |Y⟩ ancilla without measurement.The construction uses a small number of fundamental gates and is deterministic.

B. Magic state distillation

Magic-state distillation converts faulty ancillas into high-fidelity states needed for universal fault-tolerant gates. In surface-code architectures, this process can dominate resources and limit execution speed, motivating dedicated distillation factories.

  • B. Magic state distillation: Magic-state distillation combines low-fidelity ancillas and fundamental gates to produce high-fidelity ancillas suitable for logical gates.The procedure is expensive and requires very many ancillas, making it a major resource concern.
  • B. Magic state distillation: Over 90% of a single Toffoli gate’s computing effort can be consumed by ancilla distillation circuits.The analysis attributes the majority of Shor-algorithm resources to these circuits, with approximately 10 background qubits per algorithm qubit.
  • B. Magic state distillation: A distillation factory continually produces the trillions of distilled |A⟩ ancillas that a long Shor computation may require.Ancilla distillation can be the rate-limiting step in quantum circuits.
  • B. Magic state distillation: Each |A⟩ distillation circuit uses 15 lower-level |A⟩ states, takes 6 clock cycles, and occupies at most 12 logical qubits at once.The compacted circuit therefore has volume 72; two-level distillation requires 16 such circuits.
  • B. Magic state distillation: The reusable |Y⟩-ancilla S-gate circuit uses four fundamental gates and is deterministic because it requires no measurement.Unlike consuming ancilla techniques, a handful of |Y⟩ states can be distilled at startup and preserved for later use.

C. Logical phase gate without measurement

The paper replaces measurement-based S-gate construction with a deterministic circuit that reuses a |Y⟩ ancilla, reducing reliance on costly state distillation. It also frames arbitrary logical-gate synthesis as approximation with resource overhead determined by accuracy and architecture capabilities.

  • C. Logical phase gate without measurement: A reusable |Y⟩ ancilla implements the S gate deterministically using four fundamental gates, without measurement or ancilla consumption.The same construction can be reversed to create S†.
  • C. Logical phase gate without measurement: Because S gates occur frequently, reusing |Y⟩ states reduces the number of resource-intensive distillations required for the Clifford group.The approach permits distilling only a handful of |Y⟩ states at startup and preserving them for later use.
  • D. Approximating arbitrary logical gates: The Logical layer decomposes arbitrary algorithmic unitaries into circuits of fundamental gates supplied by the QEC layer, acting on application and ancilla logical qubits.Ancillas support universal computation while application qubits remain visible to the algorithm.
  • D. Approximating arbitrary logical gates: Gate synthesis seeks minimum gate and ancilla overhead for a specified approximation accuracy εapprox.Uapprox denotes the fault-tolerant circuit approximating the desired unitary U.
  • D. Approximating arbitrary logical gates: Solovay–Kitaev and Fowler sequences, phase kickback, and teleportation gates offer different accuracy, depth, ancilla, and hardware-resource tradeoffs.Method selection depends on available logical qubits for parallelism and desired performance.

VI. LAYER 5: APPLICATION

The Application layer provides an ideal programming environment in which algorithms request arbitrary gates while lower layers supply their fault-tolerant implementations. QuDOS resource analysis examines Shor factoring and quantum chemistry simulation, highlighting the dominant cost of T-gate ancilla distillation.

  • VI. LAYER 5: APPLICATION: The Application layer executes quantum algorithms using application qubits and gates, without exposing lower-layer implementation details.A designer can begin with an application and work downward to determine the required system design.
  • VI. LAYER 5: APPLICATION: Application-layer qubits exclude logical qubits devoted to distilling ancilla states needed to produce a universal gate set.These distillation qubits support the algorithm but are not visible to it.
  • VI. LAYER 5: APPLICATION: T gates can account for over 90% of the quantum computer’s resources when ancilla preparation is included.A Toffoli-gate construction illustrates how lower-layer distillation resources support a small number of application qubits.
  • B. Shor’s algorithm: The analysis applies Shor’s algorithm to factoring RSA-scale integers, including a common 1024-bit public-key length.Factoring such numbers remains nontrivial even on a quantum computer.
  • B. Shor’s algorithm: For fixed-size machines, runtime grows faster beyond 2048-bit factoring because insufficient ancilla-distillation resources create delays.About 90% of the machine should be devoted to distillation for the analyzed Shor circuit.

C. Quantum simulation

The paper evaluates fault-tolerant first-quantized molecular simulation on QuDOS and relates algorithm runtime to layered architectural timing. The simulation scales linearly with problem size under stated precision settings, while higher-layer gates incur substantial timing overhead.

  • C. Quantum simulation: The simulation targets energy eigenstates of time-independent molecular Hamiltonians in first-quantized form.The method represents electron positions in quantum registers and uses one- and two-body interactions.
  • C. Quantum simulation: Runtime scales linearly with simulation problem size rather than exponentially as in classical methods.The first-quantized formulation is general because it does not depend on a molecule’s particular structure or arrangement.
  • C. Quantum simulation: The analyzed simulations use 210 time steps and achieve at most about 3 significant figures of precision in readout.Precision scales with the number of simulated time steps.
  • D. Large-scale quantum computing: The factoring and simulation examples have similar total resource costs and comparable error-correction requirements, reflected in similar KQ products.Simulation is more compact, while Shor’s algorithm has the shorter execution time in this analysis.
  • VII. TIMING CONSIDERATIONS: Higher-layer operations take longer because they combine multiple lower-layer commands, making logical gates orders of magnitude slower than individual physical processes.QuDOS timing analysis spans physical operations through virtual gates, QEC, and logical gate construction.
  • VII. TIMING CONSIDERATIONS: Error-syndrome extraction and processing must occur on timescales comparable to logical gates or errors accumulate faster than detection.Live surface-code processing may require results within approximately 10 µs.

VIII. DISCUSSION

The discussion presents layered architecture as a modular, fault-tolerance-oriented framework that manages resources across abstraction levels. QuDOS illustrates both the promise of optical quantum-dot hardware and the severe timing overhead imposed by higher-layer operations.

  • VIII. DISCUSSION: Layer encapsulation gives each layer a distinct purpose and resource-management role, making the architecture modular and supportive of fault tolerance.Higher layers combine many operations from lower layers while hiding their implementation details.
  • VIII. DISCUSSION: Encapsulation can simplify replacing layers as quantum technologies evolve and integrating improved processes into the overall design.The framework is intended to support adaptation of subsystem technologies over time.
  • VIII. DISCUSSION: The intermediate layers are deliberately organized around fault tolerance, including control-based error mitigation and surface-code error correction.Layer 4 completes the gate set to provide arbitrary unitary operations for universal computation.
  • VIII. DISCUSSION: QuDOS combines optical quantum-dot control, solid-state integration, and mature engineering technologies as a concrete architecture platform.The platform is highlighted for its fast quantum-operation timescales and integration potential.
  • VIII. DISCUSSION: QuDOS increases operation time from nanoseconds in the Physical layer to milliseconds in the Application layer, a six-order-of-magnitude span.The overhead arises from virtual gates, quantum error correction, and higher-level gate construction.
  • VIII. DISCUSSION: The framework is presented as a transferable way to design and compare architectures for quantum technologies beyond those considered here.It provides a common language for matching quantum-computing technologies to desired applications.

Appendix A: Parallel Control of Laser Pulses in QuDOS

QuDOS combines MEMS mirrors and phase-shift masks to control parallel optical operations on quantum dots and implement surface-code measurements. The paper also analyzes resource bottlenecks for fault-tolerant factoring and first-quantized simulation.

  • Parallel optical control: Millions or billions of parallel laser pulses motivate an optical-patterning system for the quantum-dot array.The engineering analysis of this control problem is explicitly outside the paper’s detailed scope.
  • Parallel optical control: MEMS mirror arrays provide scalable control of optical patterns, with commercially demonstrated arrays containing millions of controllable units.The mirrors are proposed to address precise pattern generation across the array.
  • Parallel optical control: Phase-shift masks create diffraction-limited patterns despite quantum-dot spacing of 1 µm and laser wavelength of 920 nm.The method uses position-dependent phase shifts to produce interference from different directions.
  • Surface-code implementation: Surface-code operations are decomposed into laser-pulse sequences for cluster-state construction and measurements that create defects in the lattice.Phase-shift masks generate the pulses, while MEMS mirrors control where measurements occur.
  • Surface-code implementation: Every 2 µs, QuDOS can rearrange MEMS mirrors to update surface-code measurement locations while maintaining defect-boundary separation.The rearrangement interval follows from changing the defect configuration every d/4 lattice steps.
  • Fault-tolerant resource analysis: 90% of a quantum computer’s resources may need to support ancilla distillation for efficient Shor execution, because insufficient distillation limits algorithm speed.The result follows from comparing Toffoli-gate ancilla consumption with factory production rates.
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