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Synthesis and Optimization of Reversible Circuits - A Survey
Mehdi Saeedi, Igor L. Markov
TL;DR
Reversible-circuit research addresses information-preserving computation motivated by low-power electronics, practical transforms, and quantum technologies. This survey synthesizes methodologies, algorithms, benchmarks, tools, optimization, and technology mapping, while identifying open challenges. It concludes that existing techniques remain inadequate for important arithmetic benchmarks and that applications should motivate reversible-circuit design.
Problem
Reversible-circuit synthesis must generate compact circuits while accounting for distinctive circuit constraints, application needs, gate libraries, and cost models.
Method
The survey reviews search-based, cycle-based, transformation-based, and BDD-based paradigms, alongside exact and heuristic synthesis, optimization, and technology-mapping approaches.
Results
The survey identifies substantial progress across reversible synthesis methods but reports that existing techniques produce circuits much larger than known solutions for important arithmetic benchmarks.
Takeaways & Limitations
Reversible circuits should be studied with concrete applications in mind, especially because quantum, nano, and photonic paradigms offer improvements only in narrow circumstances.
Takeaways & Limitations
Existing reversible synthesis techniques do not perform well on important arithmetic benchmarks and produce circuits much larger than known solutions.
Abstract
from arXiv · showhide
Reversible logic circuits have been historically motivated by theoretical research in low-power electronics as well as practical improvement of bit-manipulation transforms in cryptography and computer graphics. Recently, reversible circuits have attracted interest as components of quantum algorithms, as well as in photonic and nano-computing technologies where some switching devices offer no signal gain. Research in generating reversible logic distinguishes between circuit synthesis, post-synthesis optimization, and technology mapping. In this survey, we review algorithmic paradigms --- search-based, cycle-based, transformation-based, and BDD-based --- as well as specific algorithms for reversible synthesis, both exact and heuristic. We conclude the survey by outlining key open challenges in synthesis of reversible and quantum logic, as well as most common misconceptions.
1. INTRODUCTION
Reversible computation preserves enough information to reconstruct inputs, motivating applications in low-power electronics, bit manipulation, debugging, and quantum computing. The survey organizes reversible-circuit synthesis research across methodologies, algorithms, benchmarks, tools, optimization, technology mapping, and open problems.
- Motivation: Reversible computation preserves sufficient output information to reconstruct the input, avoiding information erasure and commonly avoiding duplication.This property underlies reversible transformations and circuits.
- Motivation: Historically, reversible computation was motivated by minimizing energy loss from information erasure and duplication.The minimum energy dissipation associated with irreversible bit erasure is k_BT ln 2.
- Applications: Reversible transforms support signal processing, cryptography, and computer graphics, including storage-free swapping through three XOR operations.Bit-permutation instructions and reversible butterfly operations have also been used to improve application performance.
- Circuit model: Reversible circuits represent sequences of reversible operations and are useful in quantum computing, but reversibility prohibits loops and explicit fanouts.Read-only fanouts are compatible, while arbitrary fanouts can be simulated with ancilla lines.
- Scope: The survey covers methodologies, algorithms, benchmarks, tools, optimization, technology mapping, open problems, and future trends in combinational reversible-circuit synthesis.Its algorithmic coverage includes synthesis and related post-synthesis stages.
2. BASIC CONCEPTS
Reversible logic is built around bijective functions, reversible gates, and acyclic circuits that preserve information while supporting multiple representations and implementation strategies. The section introduces gates, ancillae, circuit constructions, representations, and quantum-circuit simulation.
- Reversible functions: A reversible Boolean function has equal numbers of inputs and outputs and implements a permutation of the input assignments.Permutations are one-to-one and onto; an example is given for a three-variable function.
- Reversible gates: The universal NCT library consists of NOT, CNOT, and Toffoli gates, while multiple-control Toffoli and Fredkin gates act as transpositions on incident bit-lines.Control lines pass unchanged, and a Toffoli target flips when its control condition is satisfied.
- Reversible circuits: Reversible circuits are acyclic, use reversible gates, and prohibit explicit fanouts and loops; arbitrary fanout can be simulated with a CNOT and an ancilla.Each gate has equal numbers of inputs and outputs with unique input-to-output assignments.
- Reversible implementations: Ancillae extend irreversible specifications to reversible circuits, while garbage lines are ancilla outputs that are not restored to constants.If an output combination occurs up to M times, g = ⌈log2 M⌉ ancillae are required.
- Representations: Reversible functions can be represented as truth tables, permutation matrices, Reed-Muller expansions, cycle products, and decision diagrams.The RM spectrum stores PPRM coefficients, while ROBDDs provide canonical Boolean-function representations.
- Quantum-circuit evaluation: Quantum-circuit simulation uses tensor products for parallel gates and ordered matrix products for cascaded gates, but direct matrix multiplication requires Ω(2^n) time and space.High-performance simulation techniques are developed to improve runtime and memory usage.
3. GENERATION AND OPTIMIZATION OF REVERSIBLE CIRCUITS
Reversible-circuit generation proceeds from reversible specifications through synthesis, optimization, and technology mapping. Exact methods provide optimality for limited cases, while heuristic paradigms trade guarantees for scalability and exploit different function representations.
- Generation and optimization: Synthesis generates a reversible circuit from a specification, followed by optional post-synthesis optimization and technology mapping into available gates.Mapping may occur before or after optimization, and ancilla availability affects decomposition cost.
- Synthesis paradigms: Exact synthesis can find optimal circuits, but practical interest in larger, nonlinear circuits has motivated heuristic methods.Representation models favor different function classes and guide decomposition into simpler functions.
- Algorithmic paradigms: Transformation-based methods iteratively make truth tables or Reed–Muller spectra more identity-like, whereas search-based methods traverse trees for reasonably good circuits.Transformation-based methods favor regular permutations; search-based methods favor irregular permutations and functions leaving many inputs unchanged.
- Algorithmic paradigms: BDD-based methods improve sharing between gate controls and scale better than other methods, but require many ancilla qubits.Other heuristics reuse conventional synthesis, ESOP cascades, or abstract group theory.
- Optimization limits: Incremental optimization can significantly improve results but cannot guarantee optimality because a circuit may contain no locally suboptimal sub-circuit.The limitation is illustrated by an NCT-optimal circuit pattern that becomes globally suboptimal as gates are added.
- Technology mapping: Multiple-control Toffoli gates can be decomposed into smaller gate sets with circuit sizes determined by available ancillae.Parallel decompositions can reduce individual-qubit manipulation at the cost of additional gates.
4. ALGORITHMS FOR REVERSIBLE CIRCUIT SYNTHESIS
The survey organizes reversible synthesis into exact, asymptotically optimal, and heuristic approaches. Exact search scales rapidly, while representation-directed heuristics and cycle-based synthesis address larger or structurally different permutations.
- 4.1. Optimal Methods: Enumerative optimal synthesis branches over possible library gates at each circuit depth, making exhaustive search grow exponentially with the optimal gate count.For n = 4, finding a 15-gate optimum would require examining approximately 3.8 × 10^22 cases by exhaustive search.
- 4.1. Optimal Methods: Optimal 3-bit synthesis builds a shared library of optimal circuits for all 8! permutations by extending stored optimal subcircuits.Optimal 4-bit methods use half-circuit storage, hash tables, relabeling, and function symmetries to reduce the search space.
- 4.1. Optimal Methods: Formal-verification techniques extend optimal synthesis using symbolic reachability, Boolean satisfiability, QBF satisfiability, and BDDs.One formulation minimizes the number of NCV stages, while another increments the number of multiple-control Toffoli gates until a circuit is found.
- 4.2. Specialized Methods: Linear reversible synthesis can be formulated as reducing a function matrix to the identity through elementary row operations over GF(2).The representation specifically encodes CNOT gates as entries in the identity matrix.
- 4.3. Heuristic Methods: Transformation-based methods select gates using truth-table or Reed–Muller-spectrum complexity, while search-based methods explore gate sequences.Transformation methods favor regular output patterns, whereas search methods handle irregular permutations and unchanged inputs more effectively.
- 4.3. Heuristic Methods: BDD-based methods scale better by sharing controls, but their requirement for many ancilla qubits limits their suitability for resource-constrained quantum hardware.The survey also describes a hybrid cycle-based framework combining cycle synthesis for irregular functions with another method for regular functions.
- 4.3. Heuristic Methods: k-cycle synthesis reduces quantum cost for large cycles using seven building blocks and dedicated algorithms for cycles shorter than six.Its cycle-based method reports best-known quantum-cost circuits for permutations without regular patterns.
- 4.3. Heuristic Methods: The maximum elementary-gate count reported for any permutation is less than 8.5n2^n + o(2^n), compared with a lower bound of n2^n/log n.The survey identifies this as the sharpest upper bound for reversible functions at the time discussed.
5. POST-SYNTHESIS OPTIMIZATION
Post-synthesis optimization reduces reversible-circuit cost by replacing equivalent sub-circuits, applying transformations, inserting ancillae, and exploiting quantum or architectural structure.
- Sub-circuit replacement: Equivalent sub-circuits can be replaced by smaller ones using windowing, sub-circuit optimization, and re-synthesis methods.Windowing selects candidate regions before re-synthesis, exact synthesis, or template matching is applied.
- Library-based optimization: Libraries store optimal small circuits as replacement rules, while generalized local transformations reduce the library size.The compact library covers all 3-bit circuits and many 4-bit circuits with fewer than six gates.
- Transformation rules: Template matching replaces an identity-pattern prefix of k gates with m−k inverse gates when k > m/2, reducing gate count.The method uses predefined reversible circuits implementing the identity function.
- Boolean simplification: K-map optimization simplifies sub-circuits whose gates share a target by representing controls and targets as Boolean functions.The approach is suited to synthesis methods generating successive gates on the same target line.
- Quantum and architectural optimization: Ancilla insertion and Hadamard-based optimization remove shared controls opportunistically, while level compaction and SWAP strategies address depth and locality.Restricted architectures require geometrically adjacent qubits, and SWAP insertion restores line ordering after moving operands.
- Quantum and architectural optimization: Minimum-SWAP search can be restricted to qubits between the interacting locations and a consecutive gate window instead of exploring all orderings.For each gate, bubble sort achieves the minimum number of SWAPs for the required ordering.
6. BENCHMARKS AND SOFTWARE TOOLS
The survey describes benchmark families, benchmark repositories, software tools, and representative arithmetic and hard functions for evaluating reversible synthesis.
- Quantum benchmarks: The survey also identifies QFT and AQFT as benchmark-related quantum circuits whose implementation cost depends on approximation and input size.A QFT of size n requires O(n^2) gates, while AQFT omits sufficiently small phase-shift gates.
- Repositories and tools: RevLib and the Reversible Logic Synthesis Benchmarks Page provide widely used reversible functions and known or suboptimal circuits.RevKit and RCViewer+ support visualization, cost analysis, equivalence checking, and circuit plotting.
- Benchmark families: Benchmark families include functions with known optimal circuits, maximal 4-bit gate counts, and Gray-code transforms.All 3-input and 4-input reversible functions have known optimal circuits in the cited families.
- Arithmetic benchmarks: Arithmetic benchmarks include adders, modulo adders, and Galois-field multipliers motivated by quantum algorithms.The nbitadder and modNadder families encode addition operations relevant to quantum computation.
- Hard benchmarks: Hard benchmarks stress synthesis algorithms with functions such as hidden weighted-bit, inc, and matrix permanent.The hidden weighted-bit function has exponential ROBDD size, while polynomial-cost implementations use logarithmically many garbage bits.
7. CONCLUSION AND FUTURE DIRECTIONS
The survey concludes that reversible and quantum synthesis still face major scalability, mapping, verification, testing, tooling, and application-motivation challenges.
- Scope and challenges: Reversible synthesis is organized into pre-synthesis optimization, synthesis, post-synthesis local optimization, and technology mapping.Technology mapping incorporates limitations of the target implementation technology.
- Scope and challenges: Existing synthesis techniques produce circuits much larger than known solutions for important arithmetic benchmarks.The survey identifies arithmetic functions as a central unresolved synthesis challenge.
- Future directions: Future work includes scalable synthesis across cost models and libraries, technology mapping, application-specific optimal synthesis, and bounds for reversible functions.The survey also calls for efficient synthesis of T-constructible permutations.
- Tools and applications: Sequential reversible computation remains weakly motivated, while quantum, nano, and photonic applications are concentrated in narrower circumstances with serious drawbacks.The survey notes quantum size limits, noise, and decoherence among those drawbacks.
- Verification and testing: Verification and testing are difficult for quantum circuits because verification approaches can approach quantum simulation complexity and measurements are nondeterministic.Fault models must match the technology; Boolean fault assumptions may be unjustified for reversible implementations.
- Quantum synthesis: Quantum-logic synthesis remains more challenging because it targets general unitary matrices and requires balancing one-qubit gates, CNOTs, depth, and ancillae.The survey specifically highlights simultaneous reduction of CNOT and one-qubit gates as a future direction.
- Physical implementation: Physical layout requires automated qubit placement and routing because quantum gates often require geometrically adjacent qubits.Current laboratory layouts are hand-optimized, motivating systematic placement methods.
- Tools and applications: Most reported design and verification tools are point tools, whereas scaling may require integrated chains of interoperating software guided by applications.The survey warns that CAD development should remain motivated by real applications.