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Staircase Codes: FEC for 100 Gb/s OTN

Benjamin P. Smith, Arash Farhood, Andrew Hunt, Frank R. Kschischang, John Lodge

arXiv:1201.4106v1cs.IT

TL;DR

High-speed optical systems need practical high-rate FEC with manageable decoder communication. The paper introduces continuously constructed staircase codes with syndrome-based decoding and evaluates a G.709-compatible design. The proposed code achieves 9.41 dB NCG at 10^-15, improves on the best G.975.1 code by 0.42 dB, and has an estimated 4.0 × 10^-21 error floor.

  • Problem

    For 100 Gb/s optical implementations, the paper addresses the efficiency challenge of LDPC message-passing decoding and the need for high-rate product-like FEC.

  • Method

    The paper introduces staircase codes combining convolutional and block-coding ideas, uses syndrome-based decoding, and proposes a G.709-compatible code with R = 239/255.

  • Results

    9.41 dB NCG at an output error rate of 10^-15 improves performance by 0.42 dB relative to the best G.975.1 code, while the estimated error floor is 4.0 × 10^-21.

  • Takeaways & Limitations

    Staircase codes provide reliable communication for streaming sources with low-latency encoding, variable-latency decoding, and efficient hardware implementation.

Abstract

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Staircase codes, a new class of forward-error-correction (FEC) codes suitable for high-speed optical communications, are introduced. An ITU-T G.709-compatible staircase code with rate R=239/255 is proposed, and FPGA-based simulation results are presented, exhibiting a net coding gain (NCG) of 9.41 dB at an output error rate of 1E-15, an improvement of 0.42 dB relative to the best code from the ITU-T G.975.1 recommendation. An error floor analysis technique is presented, and the proposed code is shown to have an error floor at 4.0E-21.

I. INTRODUCTION

The paper motivates high-speed optical FEC by contrasting LDPC message passing with more efficient syndrome-based decoding and introduces staircase codes as a high-rate product-like alternative.

  • For 100 Gb/s implementations, syndrome-based decoding of product-like codes is argued to be significantly more efficient than message-passing LDPC decoding.
  • Staircase codes combine convolutional and block-coding ideas in a continuous product-like construction.
  • The proposed syndrome-based staircase decoder is designed to provide excellent performance with an efficient implementation for high-speed fiber-optic communications.
  • The paper reviews standardized G.975 and G.975.1 optical-network FEC codes before presenting staircase codes and their error-floor analysis.
  • ITU-T G.709 framing requires candidate codes to use rate R = 239/255.

B. ITU-T Recommendation G.975.1

This section reviews G.975.1 coding schemes and frames decoder implementation complexity through data-flow, highlighting the substantial routing burden of LDPC message passing.

  • G.975.1 increases coding gain through concatenated schemes with iterative hard-decision decoding.
  • The I.3 serially concatenated BCH scheme achieves an NCG of 8.99 dB at an output error rate of 10^-15, 0.98 dB from capacity.
  • The I.5 concatenated RS–BCH product-code scheme achieves an NCG of 8.5 dB at an output-error-rate of 10^-15, 1.47 dB from capacity.
  • Decoder data-flow is used as a surrogate for implementation complexity because message-passing communication is a significant LDPC design challenge.
  • For N = 20, q = 4, and dav = 3, LDPC data-flow is approximately 480D/R, exceeding 48 Tb/s for 100 Gb/s systems.
  • Syndrome-domain product-code decoding compresses the received signal and passes at most t messages per component decoding.

2) Product Code:

Product-code decoding computes and updates row and column syndromes iteratively, reducing internal communication relative to LDPC message passing under the stated design assumptions.

  • The decoder first computes and stores row and column syndromes, then alternates row and column decoding while updating corrected positions and affected syndromes.
  • Product-code rows and columns use t1- and t2-error-correcting BCH component codes with overall rate R = R1R2.
  • The initial syndrome computation writes channel decisions to RAM while simultaneously processing them through a syndrome computation and storage device.
  • For n1 = n2 approximately 1000, r1 = r2 = 32, t1 = t2 = 3, fc approximately 400 MHz, and v = 4, product-code data-flow is approximately 293 Gb/s.
  • Syndromes provide a compressed received-signal representation, while algebraic component codes require message updates only for corrected bits.

IV. STAIRCASE CODES

Staircase codes combine recursive convolutional and block-coding ideas through successive symbol matrices, yielding a naturally unterminated product-like code. Compared with product codes, they can offer better performance at sufficiently high rates and advantages for transmitter latency.

  • Staircase codes combine recursive convolutional and block-coding ideas through an infinite sequence of binary m-by-m symbol matrices.
  • Each block places m(m −r) streaming information symbols in its leftmost columns and computes the remaining r columns as component-code parity symbols.
  • Every row and column in the staircase representation forms a valid codeword of the component code C, explaining its connection to product codes.
  • Staircase codes are naturally unterminated, so decoding strategies can be selected across a range of latencies; the paper reports that they outperform product codes.
  • At sufficiently high rates, staircase codes outperform product codes of the same rate, despite a rate difference between the constructions.
  • Staircase codes match the overall code rate in each component codeword’s effective rate, enabling a frame mapper that minimizes transmitter latency.

A. Decoding Algorithm

Staircase codes support sliding-window decoding over L consecutive received blocks. The decoder processes component codewords in reverse block order and iteratively propagates syndrome updates through the window.

  • Sliding-window decoding operates on the received bits from L consecutively received blocks, supporting decoding strategies with varying latency.
  • The graphical representation illustrates a decoder operating on a window of L = 4 blocks.
  • The decoder first decodes component codewords terminating in the latest window block, then proceeds backward toward the earliest block.
  • After decoding each group of terminating codewords, syndrome updates account for their effects on codewords terminating in the next block.

B. Multi-edge-type Interpretation

Staircase codes admit a multi-edge-type graphical interpretation that organizes their decoder structure and reliability flow. In a four-block window, previously decoded symbols effectively shorten participating component codewords.

  • The multi-edge-type interpretation represents staircase-code construction with distinct graph edge types, extending an interpretation originally used for irregular LDPC codes.
  • Figure 5 depicts the factor graph for a decoder operating on a window of L = 4 blocks, with Π representing matrix transposition.
  • Dotted variable nodes mark symbols decoded in the previous stage, whose correctness effectively shortens the component codewords in which they participate by m symbols.
  • The construction maps each staircase block to 512 rows of 510 bits for compatibility with the G.709 framing structure.
  • Each row of the compatible component code contains 990 information symbols and 32 parity symbols, forming a valid codeword of C.

V. ERROR FLOOR ANALYSIS

The analysis models error floors through stall patterns that can trap iterative hard-decision decoding, then bounds their contributions by enumerating patterns and their error probabilities.

  • Stall patterns are error configurations that lock iterative hard-decision decoding into a state with no further updates.They may be correctable by maximum-likelihood decoding.
  • A stall pattern contains codeword positions such that every involved row and column has at least t + 1 positions in the pattern.The definition includes patterns that may eventually be corrected through fortuitous decoding updates.
  • Error-floor estimation assigns spanning stall patterns to blocks and applies a union bound over the patterns involving each block.The assigned set may include positions in the current and next block, but not the preceding block.
  • The analysis evaluates minimal-stall occurrence probabilities empirically for l = 0, l = 1, and l = 2 under intentionally introduced errors.These estimates support the assumptions used to overbound the probability of a particular minimal stall.

POSITIONS ARE RECEIVED IN ERROR

Non-minimal stall contributions are bounded by classifying patterns across rows and columns, counting candidate configurations, and weighting them by their error probabilities.

  • A non-minimal stall spanning K rows and L columns is a (K, L)-stall with K ≥ 4 and L ≥ 4.If it contains l positions, then 4·max(K, L) ≤ l ≤ K·L because every involved row and column contains at least four positions.
  • Candidate (K, L)-stalls are counted by selecting rows and columns, then overbounding patterns with l positions in the induced K·L grid.The counting argument assumes K ≥ L without loss of generality and covers 4·K ≤ l ≤ K·L.
  • The contribution of each fixed K and L is estimated from the number of stall patterns and the probability that their positions are received in error.Table II reports values using ζ = 5.8 × 10^-4 and p = 4.8 × 10^-3.
  • 3.8×10^-21 is the overall estimated error floor, dominated by minimal stalls with K = L = 4.The G.709-compliant staircase code has an estimated error floor of 4.0 × 10^-21.

VI. SIMULATION RESULTS

FPGA-generated simulations evaluate the G.709-compatible staircase code against G.975 and G.975.1 codes, showing high net coding gain at a 10^-15 output error rate.

  • At an output error rate of 10^-15, the staircase code provides approximately 9.41 dB net coding gain.The simulation uses the G.709-compatible staircase code with L = 7.
  • 0.42 dB is the staircase code’s improvement relative to the best G.975.1 code.The comparison includes bit-error-rate curves for the G.975 RS code and the G.975.1 codes.
  • 0.56 dB is the staircase code’s distance from the Shannon limit at the 10^-15 output error rate.The results are generated in hardware using an FPGA implementation.

VII. CONCLUSIONS

The paper proposes staircase codes as product-like FEC codes for reliable streaming communication, including a G.709-compatible rate-R = 239/255 design evaluated by FPGA simulation.

  • Staircase codes are proposed as product-like FEC codes that provide reliable communication for streaming sources.Their construction supports low-latency encoding, variable-latency decoding, and efficient hardware implementation.
  • A G.709-compatible staircase code with R = 239/255 is presented and evaluated through FPGA-based simulation.Its reported performance is within 0.56 dB of the Shannon limit at an output error rate of 10^-15.

APPENDIX

The appendix describes lookup-based decoding for triple-error-correcting binary BCH codes, including syndrome cases, error-locator roots, and decoder data-flow. It reports a 17.1 Gb/s lookup-table data-flow for the specified parameters.

  • Syndrome-based decoding: The decoder computes syndrome-derived quantities, distinguishes decoding cases, and forms a reciprocal error-locator polynomial whose roots identify error positions.For v = 1, 2, or 3, the polynomial forms are specified in terms of syndrome values and D3.
  • Lookup-based root finding: For v = 2 or v = 3, lookup-based quadratic and cubic solvers determine the roots of the error-locator polynomial.The quadratic solver uses a suppressed quadratic, while the cubic solver uses suppressed cubic forms and lookup tables.
  • Lookup-based root finding: In either cubic-decoding case, decoding requires 2^m bits to be read from a lookup-table memory.The two cases depend on whether a^2+b is zero; both use tables with 2^m entries, each storing a pair of elements in F_2^m.
  • Data-flow: 17.1 Gb/s is the corresponding lookup-table data-flow for n = 1000, m = 10, v = 4, R = 239/255, and D = 100 Gb/s.The passage characterizes this value as small relative to data-flow from effects considered elsewhere in the decoder analysis.
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