Source-linked AI summary
Spin-Based Neuron Model with Domain Wall Magnets as Synapse
Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy
TL;DR
ANN hardware requires compact, low-power neuron and synapse implementations, while spin-mode signaling is inefficient for long-distance communication. The paper proposes a spin-CMOS hybrid architecture using clocked spin-majority neuron-synapse units and CMOS inter-neuron signaling, with physics-based modeling and variation analysis supporting its operation. Its supported conclusion is an energy-efficient, programmable architecture suitable for cognitive and Boolean computation, subject to limits from spin-diffusion length and device variation.
Problem
ANN hardware requires neuron and synapse implementations that improve compactness and power consumption.
Method
The paper combines clocked spin-majority neurons, programmable domain wall magnet synapses, and CMOS charge-mode inter-neuron signaling.
Results
The proposed spin-CMOS hybrid ANN architecture is presented as suitable for low-power, programmable cognitive and Boolean computation.
Takeaways & Limitations
The architecture localizes ultra-low-voltage neuron-synapse computation while using CMOS signaling for network-level communication.
Takeaways & Limitations
Spin diffusion length limits direct synapse fan-in and causes mismatch between input strengths across channel positions.
Abstract
from arXiv · showhide
We present artificial neural network design using spin devices that achieves ultra low voltage operation, low power consumption, high speed, and high integration density. We employ spin torque switched nano-magnets for modelling neuron and domain wall magnets for compact, programmable synapses. The spin based neuron-synapse units operate locally at ultra low supply voltage of 30mV resulting in low computation power. CMOS based inter-neuron communication is employed to realize network-level functionality. We corroborate circuit operation with physics based models developed for the spin devices. Simulation results for character recognition as a benchmark application shows 95% lower power consumption as compared to 45nm CMOS design.
I. INTRODUCTION
The paper addresses hardware challenges in ANN power consumption, integration, and throughput by proposing spin-device neuron and synapse models. Its architecture combines localized spin computation with CMOS-based inter-neuron communication.
- I. INTRODUCTION: ANN hardware must improve power consumption, integration, and throughput simultaneously.Digital designs can require large area, while analog designs can consume substantial power.
- I. INTRODUCTION: Spin devices are proposed for compact, low-power ANN neuron and synapse hardware.The proposal targets device-circuit models that jointly address compactness and power consumption.
- I. INTRODUCTION: Weighted spin-majority gates can mimic neuron-synapse functionality when operated with an appropriate clocking scheme.Domain wall magnets provide programmable spin injection strength for compact synapses.
- I. INTRODUCTION: CMOS charge-mode signaling connects neuron units because spin-mode signaling becomes inefficient over larger separations.The hybrid architecture combines localized spin-based computation with charge-mode inter-neuron communication.
II. MAJORITY GATE BASED ON LATERAL SPIN VALVE
Lateral spin valves use spin injection to switch output magnets, and their analog current-mode behavior supports majority evaluation. The paper connects these gates to neuron-like operation while motivating domain wall magnets for programmable synaptic weights.
- II. MAJORITY GATE BASED ON LATERAL SPIN VALVE: Lateral spin valves use an injecting magnet, receiving magnet, and non-magnetic channel to deliver spin current for magnet switching.The channel separates spin diffusion responsible for switching from charge-current flow in non-local injection.
- II. MAJORITY GATE BASED ON LATERAL SPIN VALVE: Non-local injection separates the spin diffusion current from the charge current, whereas local injection sends spin-polarized charge current directly into the output magnet.Both configurations are illustrated as lateral spin valve structures.
- II. MAJORITY GATE BASED ON LATERAL SPIN VALVE: Analog current-mode switching in lateral spin valves enables majority evaluation and supports all-spin-logic gates.The cited ASL examples include NAND and full-adder structures based on spin-majority evaluation.
- II. MAJORITY GATE BASED ON LATERAL SPIN VALVE: Clock-synchronized majority-gate operation resembles a neuron when the output magnet is restored after each flip.Fixed input-magnet polarization states correspond to bipolar binary synapse weights of +/-1.
- II. MAJORITY GATE BASED ON LATERAL SPIN VALVE: The design uses domain wall magnets as programmable synapses and CMOS charge-mode signaling for long-distance communication between neurons.The communication choice addresses inefficient spin-mode signaling and difficult planar interconnect layouts.
III. SPIN BASED NEURON-SYNAPSE MODEL
The model uses programmable domain-wall magnets as weighted synapses and spin-torque-switched magnets as integrate-and-fire neurons. Device geometry, clocking, and channel layout are selected to support low-power spin computation while managing switching speed and synapse mismatch.
- Domain-wall synapse: Domain-wall magnets provide programmable spin injection strength for implementing synaptic weighting.Weights are written by current-driven domain-wall motion and can use binary or multiple position-dependent levels.
- Domain-wall synapse: Spin polarization delivered to the channel varies with domain-wall position, reaching opposite extrema at the two ends and zero at the center.The central position injects equal up- and down-spin electrons, canceling net polarization.
- Spin-based neuron: The neuron sums spin-weighted inputs, presets its firing magnet on the hard axis, and then switches toward an easy-axis state set by the net channel-spin polarity.The neuron transfer function uses weighted inputs, bias, and a step-like activation; current-mode Bennett-clocking reduces the switching threshold.
- Energy-efficient operation: The unit uses a low-resistance static charge-current path through the domain-wall synapse and non-magnetic channel, while detection draws negligible transient current through the high-resistance MTJ.The operating scheme is intended to enable very small terminal voltages and ultra-low energy operation.
- Device optimization: Increasing ground-lead resistance improves spin-injection efficiency, while smaller output-magnet volume and higher Hk improve switching speed and easy-axis restoration.These improvements require corresponding geometric and resistance choices to preserve injection efficiency.
- Modular neuron-synapse unit: The centre-surround layout limits direct fan-in because spin polarization decays along the metal channel and produces location-dependent synapse mismatch.The text reports up to ~32 directly combined synapses for copper with λ~1 µm, while 32-input neurons show prominent mismatch.
IV. SYSTEM INTEGRATION
Because short spin-diffusion lengths limit spin-mode network connectivity, the design converts local spin firing into CMOS charge-mode signals for inter-neuron communication. This preserves local spin-device operation while supporting network-level integration.
- Inter-neuron communication: CMOS charge-mode signaling interconnects the spin-based neuron-synapse modules because limited spin diffusion length prevents efficient spin-mode network connectivity.A dynamic CMOS latch converts spin-mode firing information into charge-mode signals.
- System-level correspondence: The proposed architecture is intended for artificial-neural-network hardware rather than exact biological functional mimicry.Its biological correspondence is therefore architectural rather than a claim of identical neural functionality.
V. SIMULATION FRAMEWORK
The simulation framework couples spin transport and magnet dynamics to model spin-based neuron–synapse units, including domain-wall-magnet synapses and a two-dimensional network extension.
- Neuron simulation: The neuron model is simulated by self-consistently solving transport and magnet-dynamics equations using a four-component spin-circuit model.Channel transport follows the Valet–Fert spin-diffusion model, while nano-magnet dynamics are obtained from the Landau–Lifshitz–Gilbert equation.
- Transport model: The non-magnetic channels and leads are represented by π-conductance matrices with shunt and series components.The shunt and series conductances are parameterized using channel geometry, resistivity, spin-diffusion length, and contact length.
- Network extension: The spin-circuit framework maps non-local spin transport and nano-magnet interactions into an equivalent circuit model.The approach is extended to a 2-D neuron–synapse grid composed of 10nm x 10nm channel sections.
- Self-consistent dynamics: Magnetization-dependent circuit matrices require spin-diffusion transport to be solved self-consistently with Landau–Lifshitz–Gilbert dynamics at each grid point.This couples the local magnetic state of the two-dimensional grid to the simulated transport response.
- Synapse model: Domain-wall-magnet synapses are modeled as two parallel nano-magnets with opposite polarities, with area determined by domain-wall location and therefore representing the weight.The domain-wall-magnet model is benchmarked against experimental data through domain-wall velocity as a function of charge-current density.
VI. NETWORK SIMULATION
The network simulation evaluates spin-CMOS character recognition, variation tolerance, neuron reliability, and performance against 45nm CMOS implementations. It uses edge extraction and pattern matching while examining device variability and design trade-offs.
- Benchmark application: Character recognition is divided into edge extraction and pattern matching, with first-stage neurons processing binary image pixels along four directions.The resulting four binary patterns form a one-dimensional representation that is sent to output neurons for classification among 36 alphanumeric characters.
- Benchmark application: Handwriting-style variation produces slight barcode changes that an ANN can tolerate, with further tolerance obtainable by training on different input styles.The barcode represents extracted horizontal-edge information before classification.
- Variation analysis: Critical DWM variation sources include interface oxide thickness, cross-section area, and domain-wall location, which affect injected current, spin polarization, and synapse-weight precision.The text identifies oxide-thickness mismatch and programming inaccuracy as sources of weight error, while noting that atomic layer deposition can precisely control oxide thickness.
- Variation analysis: <10% of the spin-current injection range is the stated condition under which the noisy transition zone can be ignored in overall network performance.Because the spin-current range depends linearly on average synapse current, noise limits how far synapse current can be reduced for lower power.
- Variation analysis: 25% 3σ variation in critical magnet parameters spreads neuron relaxation times, while lower volume and higher Hk reduce the spread and support higher reliable operating frequency.The analysis varies input current from 20µA to 0.5µA across synapse-current combinations.
- Design performance: The spin-CMOS hybrid implementation achieves low power and small area comparable to the analog ANN, whereas the digital 45nm CMOS design incurs larger area and power.The comparison uses digital CMOS with programmable latches and full adders, and analog CMOS with memristive synapses.
- Design performance: The proposed design combines localized ultra-low-voltage spin neuron–synapse operation with CMOS-based inter-neuron signaling and power-gating strategies for highly integrated programmable computation.The paper identifies cognitive and Boolean applications as supported targets for the spin-CMOS hybrid architecture.