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Implementation of Energy Efficient Single Flux Quantum (eSFQ) Digital Circuits with sub-aJ/bit Operation
Mark Hans Volkmann, Anubhav Sahu, Coenrad Johan Fourie, Oleg A. Mukhanov
TL;DR
Conventional RSFQ's resistor-based dc bias creates dominant static dissipation, motivating lower-energy logic. This paper experimentally demonstrates eSFQ shift registers and demultiplexers, reporting ~0.8 aJ/bit for shift registers and over two orders of magnitude lower energy per bit than the same circuits in RSFQ.
Problem
Conventional RSFQ's resistor-based dc bias dissipates substantial static power independent of circuit activity, while computing needs greater energy efficiency.
Source: §1 · p. 1Method
The paper experimentally implements eSFQ circuits using superconducting dc bias dividers and passive phase shifters to address static and dynamic power dissipation.
Source: §1 · p. 2Results
~0.8 aJ/bit was achieved by demonstrated eSFQ shift registers, over two orders of magnitude better than the same circuits in conventional RSFQ.
Source: §5 · p. 22Takeaways & Limitations
eSFQ retains RSFQ's locally controllable SFQ clock, which the authors identify as advantageous for scaling and managing circuit power.
Source: §5 · p. 23The 16-bit deserializer had comparatively low bias margins, attributed to test-structure complexity and an ill-designed monitor setup.
Source: §4.2 · p. 22
Abstract
from arXiv · showhide
We report the first experimental demonstration of recently proposed energy-efficient single flux quantum logic, eSFQ. This logic can represent the next generation of RSFQ logic eliminating dominant static power dissipation associated with a dc bias current distribution and providing over two orders of magnitude efficiency improvement over conventional RSFQ logic. We further demonstrate that the introduction of passive phase shifters allows the reduction of dynamic power dissipation by about 20%, reaching ~0.8 aJ per bit operation. Two types of demonstration eSFQ circuits, shift registers and demultiplexers (deserializers), were implemented using the standard HYPRES 4.5 kA/cm2 fabrication process. In this paper, we present eSFQ circuit design and demonstrate the viability and performance metrics of eSFQ circuits through simulations and experimental testing.
1. Introduction
The energy demands of high-end computing motivate alternatives to conventional RSFQ, whose resistor-based bias network causes dominant static power dissipation. This paper reports the first experimental eSFQ circuits, targeting lower static and dynamic power while retaining RSFQ characteristics.
1. Introduction
- Conventional RSFQ's resistor-based dc bias network dissipates static power regardless of circuit activity, at a level roughly 100 times its switching power.The introduction identifies this dissipation as a barrier to energy-efficient, energy-proportional computing.Source: §1 · pp. 1–2
- Earlier energy-efficient SFQ approaches had been explored, but eSFQ had only been discussed theoretically before this experimental work.The paper situates eSFQ among reduced-static-power RSFQ, RQL, and ERSFQ approaches.Source: §1 · p. 2
- eSFQ shift registers and demultiplexers were experimentally demonstrated, with static-power elimination yielding over two orders of magnitude lower overall circuit power than conventional RSFQ.The paper reports the first experimental demonstration of eSFQ circuits.Source: §1 · p. 2
- Passive superconducting phase shifters reduce bias current and dynamic power, while managing SFQ clock distribution can stop a circuit with its internal state maintained.The paper presents both as routes toward energy-proportional computing.Source: §1 · p. 2
2. Principles of eSFQ logic
Conventional RSFQ power has static and switching-related dynamic components, and reducing static power with low-voltage resistive biasing trades stability against operating frequency. eSFQ instead uses Josephson-junction current limiters and clock-synchronized bias terminals to eliminate static dissipation without large averaging inductors.
2.1. Power dissipation in RSFQ logic
- For typical RSFQ bias voltage (~2.6 mV) and clock frequencies of tens of GHz, static-to-dynamic power ranges from one to two orders of magnitude; lowering bias voltage can constrain operating frequency through the branch L/R time constant.In conventional RSFQ, resistors distribute dc bias, while SFQ switching events dissipate dynamic power.Source: §2.1 · pp. 3–4
2.2. Eliminating static power dissipation
- ERSFQ and eSFQ replace resistor-based dc bias distribution with Josephson-junction limiters, which can transmit their critical current with zero voltage drop.ERSFQ requires large averaging inductors and feeding JTLs; eSFQ was proposed to remove those requirements.Source: §2.2 · pp. 4–5, §2.3 · p. 6
- eSFQ connects bias terminals to the clock net so their phases change together each period, keeping phase across limiting junctions unchanged after bias ramp-up.The limiting junctions must remain sub-critical and not switch during circuit operation.Source: Figure 3 · p. 6, §2.3 · p. 7
- Clocked decision-making pairs provide suitable eSFQ bias terminals because one junction switches per clock interrogation and the pair's total phase advances by 2π.This common phase advance allows bias injection at the DMP while synchronizing it to the clock.Source: Figure 3 · p. 6
3. Design of eSFQ demonstrator circuits
The demonstrator design adapts RSFQ cells for eSFQ biasing and applies the approach to shift registers and deserializers. The shift-register designs explore damping and magnetic flux bias to balance operating margins, clock speed, and energy.
3. Design of eSFQ demonstrator circuits
- The design moves D-cell bias injection to the decision-making pair (DMP), whose clock-driven phase increment supports eSFQ biasing.This conversion leaves the D-cell storing logic “1” after initial bias ramp-up; some cells, such as conventional T flip-flops, require a supply-free ballistic design instead.Source: §3 · pp. 7–8, Figure 4 · p. 8
- The first eSFQ demonstrators were a shift register and a demultiplexer, selected as clocked circuits suited to the SFQ clock network.The shift register is a common technology benchmark, while the demultiplexer has practical relevance to superconducting ADCs.Source: §3 · p. 8
3.1 Design of eSFQ Shift Registers
- In eSR, the counterflow clock passes from CIn to COut if J1 switches, or produces an output at DOut if J2 switches.After bias ramp-up, the cell initially stores “1”; the first clock transfers that state to the output and leaves the cell storing “0.”Source: §3.1 · p. 9, Figure 5 · p. 9
- A 4-bit eSR achieved ±24% critical and ±34% bias margins with overdamped J1, which is less likely to switch before J2.The critical margin concerns J1 area across all four cells; the bias margin concerns the entire test structure.Source: Figure 6 · p. 10
- Overdamping J1 improves eSR margins but slows switching, causing data-dependent clock skew and potentially halving maximum clock frequency.The design therefore sought equally shunted junctions while preserving parameter margins.Source: §3.1 · pp. 10–11
- At a 20 GHz clock and center of the operational bias region, simulated 16-bit eSFQ shift registers consumed ~1.0 aJ/bit with eSR and ~0.8 aJ/bit with MeSR; both reproduced the input pattern.MeSR’s dc flux bias redirects storage-loop current, and one flux-bias line serves the entire shift register regardless of its length.Source: §3.1 · p. 11, Figure 8 · p. 13
- The eDES deserializer uses a dual-port D flip-flop for serial shifting and parallel readout; an n-bit design divides serial input into n parallel streams.Its per-bit switching energy approaches that of MeSR for long deserializers; the energy is not meaningfully specified independently of deserializer length.Source: §3.1 · pp. 13, 15
4. Experimental Evaluation
The evaluation fabricated eSFQ shift registers and deserializers on five chips, then tested their operation and bias margins. All tested structures passed functional testing, while measured margins and their dependence on magnetic bias varied across designs.
4.1. Sample Layout and Fabrication
- Twelve test structures were assembled across five 5 x 5 mm2 chips, including 16- and 32-bit shift registers and 4-, 8-, and 16-bit deserializers.Layouts varied bias-line inductance and current-injection fan-in; the fabricated cells included eSR, MeSR, and eDES designs.Source: §4.1 · pp. 15, 17, Figure 10 · p. 16, Figure 11 · p. 17
4.2. Test Results
- All tested structures passed functional testing across the applied patterns, including randomly generated data and clock patterns.Shift-register operation was checked by transmission delay, while deserializers were checked by loading an n-bit pattern and verifying the parallel readout after a read pulse.Source: §4.2 · pp. 18, 20, Figure 13 · p. 19, Figure 14 · p. 19
- Measured margins roughly matched simulations and supported the authors’ conclusion that the designs are robust and scale well.The simulations used 4-bit high-speed testbeds rather than the actual devices and their periphery.Source: §4.2 · p. 21
- MeSR shift registers operated only with magnetic bias, and the 32-bit register had better measured margins than the 16-bit circuit.The dataset was too small to establish a definite length trend; the authors attribute the difference tentatively to reduced influence from adjacent RSFQ test I/O.Source: Figure 15 · p. 20, §4.2 · p. 21
- Magnetic flux bias doubled the measured bias margins of the 16-bit deserializer, while the 8-bit structure did not show the same symmetry.Deserializers also operated without magnetic flux bias; the 8-bit asymmetry may indicate greater susceptibility to the periphery.Source: §4.2 · p. 21, Figure 16 · p. 21
- The 16-bit deserializer showed comparatively low margins, potentially depressed by its complex monitor setup and peripheral cells biased from a single pin.The study did not conclusively identify effects of bias-line inductance or bias-current fan-in within the investigated parameter ranges.Source: §4.2 · p. 22
5. Discussion and Conclusions
The demonstrated eSFQ shift registers reached about 0.8 aJ per bit, over two orders of magnitude better than the same circuits in conventional RSFQ. The discussion also weighs phase-shifter benefits and fabrication choices against cryocooling costs and the scope of projected system-level advantages.
5. Discussion and Conclusions
- The eSFQ shift registers reached ~0.8 aJ/bit, over two orders of magnitude better than the same circuits implemented in conventional RSFQ logic.The reported bit energy includes integrated SFQ clock lines.Source: §5 · p. 22
- Passive phase shifters reduced gate bias and dynamic power dissipation by about 20%, without limiting maximum clock frequency.The alternative stronger-damping approach is simpler to implement but reduces maximum operating speed; the phase-shifter approach requires added elements such as a flux bias line or π-junctions.Source: §5 · p. 22
- Using π-junction phase shifters would require incorporating ferromagnetic materials into a conventional superconducting fabrication process.The authors expect superconductor–ferromagnetic phase shifters to be preferable for eSFQ circuits.Source: §5 · p. 23
- The shift-register design uses five junctions per bit, excluding the passive bias-limiting junction, versus eight per bit for RQL and 200 junctions for an 8-bit low-power RSFQ circuit.A 16-bit eSFQ shift register contains 80 junctions.Source: §5 · p. 23
- eSFQ retains conventional RSFQ’s high speed, throughput, dc bias, controllable SFQ clock, and lossless interconnects, which the authors connect to scaling and energy-proportional computing.They identify the ability to manage clock distribution as a prerequisite for energy-proportional processors.Source: §5 · p. 23
- With a 360 W/W cryocooler, the demonstrated circuit’s energy is estimated at ~290 aJ/bit; the authors say practical power-density advantages require further study.The discussion notes that cryocooling efficiency depends on cryocooler size and that comparative heat removal and operating temperatures remain to be accounted for.Source: §5 · p. 23