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Overview of Beyond-CMOS Devices and A Uniform Methodology for Their Benchmarking
Dmitri E. Nikonov, Ian A. Young
TL;DR
Beyond-CMOS devices needed a consistent and reproducible benchmarking framework because prior comparisons lacked common methods, details, and assumptions. This paper establishes simple, transparent estimates for circuit area, switching time, and switching energy, then compares NRI logic devices. The discussion identifies voltage-controlled switching as important for competitive spintronic logic and notes that current benchmarks omit non-volatility and reconfigurability.
Problem
Prior beyond-CMOS benchmarking lacked a uniform methodology, reproducible calculation details, and consistent assumptions, limiting reliable and fair comparison.
Method
The paper establishes a simple, reproducible, transparent methodology for estimating area, switching time, and switching energy across standard circuits and devices.
Results
Electronic devices benefit most from reduced operating voltage, tunneling FETs appear leading, and spintronic devices have an advantage for complex logic functions and voltage-controlled switching.
Takeaways & Limitations
Beyond-CMOS comparisons should use common, reproducible benchmarks, while exploiting non-volatility and reconfigurability requires new circuit types beyond current benchmarks.
Takeaways & Limitations
Current benchmarks do not capture non-volatility and reconfigurability, and the paper’s benchmark accuracy is limited because device structures and characteristics are not yet firmed up.
Abstract
from arXiv · showhide
Multiple logic devices are presently under study within the Nanoelectronic Research Initiative (NRI) to carry the development of integrated circuits beyond the CMOS roadmap. Structure and operational principles of these devices are described. Theories used for benchmarking these devices are overviewed, and a general methodology is described for consistent estimates of the circuit area, switching time and energy. The results of the comparison of the NRI logic devices using these benchmarks are presented.
1. Introduction
The paper addresses inconsistent and insufficiently transparent benchmarking of beyond-CMOS logic devices by establishing a uniform methodology for comparing circuit area, switching time, and switching energy. It also identifies limits of these benchmarks, including their omission of non-volatility, reconfigurability, standby power, and alternative circuit architectures.
- Motivation: Earlier benchmarking lacked a uniform methodology, reproducible calculation details, and consistent assumptions about device operating conditions and characteristics.The paper therefore targets reliable metrics and fair device comparisons.
- Benchmark scope: The study benchmarks an inverter with fanout 4, a 2-input NAND gate, and a 32-bit adder using area, switching time, and switching energy.These standard circuits enable one-to-one comparison across devices.
- Interpretation: The benchmarks permit comparison of beyond-CMOS computing with mainstream CMOS computing, while relative device benefits may be more reliable than absolute metric values.The paper emphasizes uniformity and transparency rather than claiming accurate absolute predictions at this early research stage.
- Limitations: Standard benchmarks omit utility from non-volatility and reconfigurability, may overlook devices suited to different circuit roles, and measure active rather than standby power.Spintronic devices may require different circuits to exploit normally-off operation, and future research must address these limitations.
- Methodology: The methodology applies the same assumptions, relations, and schemes across applicable devices, lists equations and parameters, and provides Matlab code for reproducibility.The authors favor simple analytical expressions over simulations because device structures and operational characteristics are not yet firmed up.
- Scope and assumptions: The scope is limited to digital Boolean logic, excluding analog, mixed-signal, non-Boolean, and neuromorphic computing; device manufacturability and integration success are not evaluated.Devices are assumed to operate as intended, with optimistic material, lithography, and structure assumptions that do not reach physical limits.
3. Computational variables and device classification
The paper classifies beyond-CMOS devices by computational variables representing inputs, outputs, internal state, and switching controls, then describes included device families and their operating principles.
- Computational variables: The variable set includes charge, current, and voltage; electric dipoles; magnetic moments or polarized spins; orbital states; and collective electron states.
- Computational variables: Mechanical position, light intensity, and signal timing are identified as additional computational variables but are not used in this study.
- Computational variables: Computational variables encode a device’s internal state, input and output signals, and switching controls, including clocking.
- Device classification: Transducers convert incompatible variables between stages, including electronic signals and spintronic signals.
- Device classification: Devices are classified by computational variables serving as inputs, outputs, or internal state, with subclasses assigned by the phenomenon underlying operation.
- Device families: CMOS switches a channel barrier through gate voltage, while TFETs use band-to-band tunneling and graphene pn-junctions switch electron transmission or reflection.
5. Constants and parameters
The benchmarking analysis uses fundamental physical constants and material constants collected in dedicated parameter tables.
- The analysis uses constants and parameters collected in Tables 2 and 3.
6. Layout principles
Layout estimation uses scalable design rules and contacted-line pitches to derive circuit areas consistently across CMOS and beyond-CMOS devices.
- Layout principles: The paper proposes a simple, general method for estimating the areas of beyond-CMOS circuits.
- Layout principles: F is the DRAM half-pitch and is set to 15nm in this study; device parameters are then taken from the corresponding technology assumptions.
- Layout principles: Scalable design rules specify minimum element widths and spacings using the maximum mask-misalignment unit λ, typically λ = F/2.
- Layout principles: Circuit layouts are drawn for the considered devices, with areas estimated by counting pitches of important lines and using designated mask layers.
- Layout principles: 8λ is the contacted pitch for important circuit lines, so the paper adopts the minimum contacted pitch as 8λ = 4F.
7. Circuit area estimation
The paper estimates circuit areas from device geometry, layout overheads, and architecture-specific assumptions, then compares transistor-like and spintronic implementations. Spintronic devices can have larger intrinsic elements yet smaller adder areas because of richer functionality.
- Area-estimation methodology: Device and circuit sizes are calculated from Table 5 parameters, layout dimensions, and empirically derived overhead factors.Gate area is estimated from layout-cell length and width, then multiplied by a gate overhead factor.
- Transistor-like devices: The fanout-4 inverter area is modeled as M_gate multiplied by 2p_m(3p_m + w_X).The inverter uses the standard transistor width and equal n- and p-transistor widths.
- Transistor-like devices: SpinFET cell area matches CMOS, whereas BisFET circuits are larger because of additional device elements.The BisFET and SpinFET comparisons are illustrated in Figures 31 and 32.
- Adder circuits: The 32-bit adder area is obtained by multiplying the one-bit adder area by 32, with architecture-specific gate or element counts.The modeled one-bit structures include XOR/AND/OR gates, NANDs and COPY elements, MUXes, or majority gates.
- Comparison: Intrinsic spintronic elements are larger than electronic ones, but spintronic adders are smaller because majority gates provide richer functionality.The area estimate is applied across the considered spintronic devices, with device-specific majority-gate counts.
8. General considerations for switching time and energy
Switching benchmarks depend strongly on voltage, current, capacitance, and interconnect assumptions. The study reports optimistic 10mV estimates alongside more realistic 100mV calculations while omitting some power-distribution contributions.
- Benchmark inputs: Switching time and energy depend strongly on the voltage and current used by each device.Device-level simulations are needed to obtain the benchmark inputs, and changes in those inputs can change overall conclusions.
- Power accounting: The estimates neglect dissipated power in low-voltage supply sources and power-and-ground distribution networks.The authors state that correctly accounting for this potentially significant contribution is beyond the study’s scope.
- Capacitance modeling: Capacitances are treated consistently using an advanced gate stack, device-dependent adjustment factors, parasitics, contacts, and interconnects.BisFET and SpinFET capacitances are increased for additional elements, while tunneling devices receive smaller factors for lower on-state gate charge.
- Interconnect modeling: Interconnect capacitance is proportional to wire length and is estimated using line capacitance between ground planes and neighboring lines.For F=15nm, the reported values are c_il = 126 aF/μm and C_ic = 37.8 aF.
9. Switching time and energy for electronic devices
Electronic-device benchmarks use simple capacitance-current equations for intrinsic devices and interconnects, then combine empirically scaled gate costs into inverter, NAND, XOR, and adder estimates.
- Device-level estimates: Transistor-like devices are benchmarked uniformly using intrinsic capacitance, on-current, switching time, and switching energy.The intrinsic expressions are t_int = C_devV_dd/I_dev and E_int = C_devV_dd^2.
- Interconnect estimates: Interconnect delay and energy are estimated from interconnect capacitance, supply voltage, and device on-current.The interconnect delay includes a 0.7 factor, with an additional factor of 2 applied in the interconnect treatment.
- Graphene devices: Graphene-device resistance combines collimation and contact resistance, with contact resistance inversely proportional to graphene width.The number of propagating quantum modes determines collimation resistance, while device current is set by total resistance.
- Logic-gate estimates: Circuit delay and energy are assembled from intrinsic and interconnect contributions using empirical factors for FO4 inverters, NAND2, and XOR gates.The NAND2 energy includes a factor of 2 for two transistors in the pull-up or pull-down networks.
- Adder estimates: For a 1-bit full adder, delay and energy combine the costs of two XOR gates and three NAND-equivalent gates.The estimates use t_xor = 3t_nand and E_xor = E_nand.
- Adder estimates: GpnJ adders contain four MUXes, but the carry critical path traverses one MUX; one-bit benchmarks are then multiplied by 32.The GpnJ energy expression accounts for ten switched MUX-equivalent contributions.
10. Common methods of magnetization switching
The study models current- and voltage-controlled magnetization switching using device-specific magnetic, electrical, and multiferroic parameters. It applies these estimates to spintronic benchmarks while leaving some switching methods and energy contributions outside scope.
- Current-controlled switching: Current-controlled switching is modeled through magnetic energy barriers, critical current density, switching current, switching time, and switching energy.The switching energy is calculated as E_stt = I_devV_ddt_stt.
- Device assumptions: Material-specific assumptions include CoFe-like parameters for in-plane switching, CoPtCrB-like parameters for perpendicular STT, and BFO for multiferroic switching.The paper specifies aspect-ratio assumptions for the modeled nanomagnets.
- Voltage-controlled switching: Voltage-controlled switching is described using multiferroic exchange bias, which produces an effective magnetic field at the interface.The total switching time combines ferroelectric charging time with magnetization switching time.
- Voltage-controlled switching: Piezoelectric switching uses polarization-induced strain and interfacial stress to switch magnetization through the magnetostrictive effect.The example uses PMN-PT and assumes hysteretic switching behavior.
- Scope boundary: The study does not cover switching by voltage changes of surface anisotropy.It also notes that none of the present devices are envisioned to use linear magnetoelectric switching.
- Scope boundary: Benchmark energy includes driving-transistor contributions but excludes reading circuits such as sense amplifiers.The omitted reading contribution can become significant in some cases.
11. Switching time and energy for spintronic devices
The paper extends intrinsic switching estimates to spintronic circuits by selecting device-specific current- or voltage-controlled mechanisms and accounting for interconnects. Circuit delay and energy are then derived for inverters, NAND gates, full adders, and majority-gate logic.
- Device-specific estimates: Device-specific switching assumptions determine which intrinsic delay and energy estimates are used for each spintronic device.The benchmarking distinguishes current-controlled and voltage-controlled magnetization switching.
- STT/DW: For STT/DW, domain-wall motion sets intrinsic switching time, while supplied current determines switching energy.The intrinsic time is the time required for the domain wall to move past the magnetic tunnel junction.
- Circuit composition: Circuit delay combines intrinsic device and interconnect delays, while circuit energy combines their corresponding energy contributions.For short interconnects, the interconnect is assumed to take the same switching time as the gate and require no additional energy.
- Circuit composition: A NAND gate implemented by a three-input majority gate retains the intrinsic switching time but scales energy with three inputs, except for NML.For NML, energy is spent on clocking the whole device rather than separate inputs, so the factor of three is absent.
- Circuit composition: A 1-bit full adder is modeled from its required majority gates, with delay based on the critical path and energy based on the gate count.The treatment also accounts for an additional interconnect required by a full adder.
12. Comparison of devices
The comparison evaluates inverter, NAND, and 32-bit-adder energy-delay trade-offs across switching mechanisms and compares the resulting benchmarks with earlier NRI results. Voltage-controlled spintronic switching improves projections enough for several spintronic circuits to become competitive with electronic circuits.
- Energy-delay comparison: At 100mV, switching energy is 10 times higher than at 10mV for the current-controlled case.Lowering supply voltage could reduce energy but may encounter critical-current fluctuations.
- Energy-delay comparison: Voltage-controlled switching significantly improves the intrinsic speed and energy of spintronic devices, making spintronic circuits competitive with electronic ones.The exceptions are ASLD, STT/DW, and STO logic, which inherently rely on spin torque.
- Energy-delay comparison: Magnetostrictive voltage-controlled switching produces somewhat better switching energy than multiferroic voltage-controlled switching.The benchmark selects magnetostrictive switching for devices that support it.
13. Computational throughput and power dissipation
The paper defines computational throughput under fixed area and capped dissipated power, then compares beyond-CMOS devices with high-performance CMOS. Heterojunction TFET leads throughput, while some tunneling FETs and spintronic devices offer lower-power alternatives.
- Throughput metric: Computational throughput measures useful integer operations per second per unit area, with 32-bit additions used as the workload.The study uses a ripple-carry adder activity factor of 1/32.
- Scope and assumptions: The throughput analysis omits pipelining, long interconnects, clock distribution, other system-on-chip power, and leakage power.These omissions constrain interpretation of the reported power and throughput estimates.
- Throughput metric: Capped throughput is defined as min(1, P_cap/P_diss) times the uncapped adder throughput under fixed area.The power-density cap is set to 10 W/cm^2.
- Device comparison: Only the heterojunction TFET is expected to provide higher throughput than high-performance CMOS while dissipating less power.BisFET and SpinFET have lower but comparable throughput at the same power.
- Device comparison: Other tunneling FETs and a few spintronic devices provide comparable throughput at significantly lower power.The relationship between capped throughput and dissipated power is shown in Figure 52.
- Device comparison: Spintronic logic additionally offers non-volatility and reconfigurability, which are not captured by the current benchmarks.Using these advantages requires designing new circuit types.
15. Conclusions
The paper presents simple, general estimates for benchmark parameters that apply across multiple NRI devices. It aims to provide a consistent and reproducible basis for beyond-CMOS benchmarking and solicit broader consensus.
- Conclusions: The proposed estimates apply to multiple devices and provide a consistent, reproducible methodology for benchmarking NRI devices.The methodology is intentionally simple but general.
- Conclusions: The authors solicit researcher input and suggestions toward uniform consensus on beyond-CMOS benchmarking.The paper frames consensus-building as an ongoing field effort.
20 M. J. Gilbert, “Performance Characteristics of Scaled Bilayer
The section’s supplied material is a related-work bibliography covering beyond-CMOS device concepts, spin-based logic, graphene, excitonic devices, magnetic technologies, and CMOS scaling.
- Graphene devices: The references include graphene and bilayer graphene devices proposed for post-CMOS logic.
- Spin and magnetic logic: Spin-based approaches span spin transistors, spin-torque majority gates, all-spin logic, spin-wave buses, and magnetic tunnel-junction logic.
- Magnetic technologies: The bibliography also covers magnetic domain-wall logic, magnetic quantum cellular automata, multiferroic QCA, and magnetoelectric effects.
- Other beyond-CMOS devices: Other cited alternatives include excitonic transistors and switches, single-exciton logic, Mott-transition transistors, and few-electron transistors.
- Benchmarking context: The references include benchmarking frameworks and conventional CMOS scaling sources relevant to evaluating emerging devices.