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Integration of nanoscale memristor synapses in neuromorphic computing architectures
Giacomo Indiveri, Bernabe Linares-Barranco, Robert Legenstein, George Deligeorgis, Themistoklis Prodromakis
TL;DR
Conventional neuro-computing often lacks close ties to neuroscience and does not fully exploit biological efficiency, variability, and unreliable components. The paper reviews memristor-based architectures and proposes a hybrid memristor-CMOS synapse that emulates synaptic biophysics and temporal dynamics. It argues that this circuit supports brain-inspired probabilistic computing robust to variability and fault-tolerant by design.
Problem
Neuro-computing architectures have often ignored biological neural systems' low power and robust computation with massively parallel, variable, unreliable components.
Method
The paper reviews memristor-based neuro-computing architectures and proposes a hybrid memristor-CMOS circuit that directly emulates synaptic biophysics and temporal dynamics.
Results
The proposed circuit combines dense, low-power long-term synaptic weight storage with detailed synaptic biophysics and computational properties of neural systems.
Takeaways & Limitations
The circuit is presented as a building block for brain-inspired probabilistic computing designed to be robust to variability and fault-tolerant.
Takeaways & Limitations
Memristors exhibit high variability, and scaling down makes unreliable and stochastic behavior unavoidable.
Abstract
from arXiv · showhide
Conventional neuro-computing architectures and artificial neural networks have often been developed with no or loose connections to neuroscience. As a consequence, they have largely ignored key features of biological neural processing systems, such as their extremely low-power consumption features or their ability to carry out robust and efficient computation using massively parallel arrays of limited precision, highly variable, and unreliable components. Recent developments in nano-technologies are making available extremely compact and low-power, but also variable and unreliable solid-state devices that can potentially extend the offerings of availing CMOS technologies. In particular, memristors are regarded as a promising solution for modeling key features of biological synapses due to their nanoscale dimensions, their capacity to store multiple bits of information per element and the low energy required to write distinct states. In this paper, we first review the neuro- and neuromorphic-computing approaches that can best exploit the properties of memristor and-scale devices, and then propose a novel hybrid memristor-CMOS neuromorphic circuit which represents a radical departure from conventional neuro-computing approaches, as it uses memristors to directly emulate the biophysics and temporal dynamics of real synapses. We point out the differences between the use of memristors in conventional neuro-computing architectures and the hybrid memristor-CMOS circuit proposed, and argue how this circuit represents an ideal building block for implementing brain-inspired probabilistic computing paradigms that are robust to variability and fault-tolerant by design.
1. Introduction
Neuro-computing spans abstract artificial neural networks and hardware that reproduces neural biophysics, while emerging nanotechnologies offer compact, low-power devices for neuromorphic systems. The paper reviews these approaches and proposes a hybrid memristor-CMOS circuit that emulates real synapses.
- Neuro-computing links brain information processing with computation, while neuromorphic engineering implements neural processing and sensorimotor systems in VLSI circuits.
- Conventional large-scale systems can incur substantial power costs, including about 1 kW per BrainScaleS wafer and about 90 kW for another simulation engine.BrainScaleS implements about 262 thousand I&F neurons and 67 million synapses while operating about 10000 times faster than biology.
- Neurogrid instead models over one million neurons connected by billions of synapses in real time using about 3 W.Its CMOS-based neuromorphic approach directly emulates cortical biophysics and connectivity.
- Nanoscale ReRAM offers infinitesimal dimensions, multiple bits per element, and minuscule write energy for extending standard CMOS technologies.
- The paper reviews integration of nanoscale synaptic devices and proposes a hybrid memristor-CMOS circuit emulating real-synapse behavior, including temporal dynamics.
2. Solid-state memristors
Memristors store history-dependent resistive states through ionic or vacancy displacement, providing a physical analogy to synaptic dynamics. TiO2 devices demonstrate polarity-dependent switching, multiple states, nanoscale arrays, and pulse-programmable synaptic behavior.
- Memristors are ReRAM memory-resistors whose functional signature is a pinched hysteresis loop under bipolar periodic excitation.Their state reflects inertia in a physical property that lags changes in the driving mechanism.
- Chemical synapses and memristors are compared through neurotransmitter discharge and displacement of ionic species within an inorganic barrier.TiO2-based models associate distinct resistive states with oxygen-vacancy displacement between TiO2 phases.
- Positive voltage sweeps switch TiO2 crossbar devices from HRS to LRSs, whereas inverted polarity reverses the trend.
- -3 V, 1 µsec pulses program a single memristor into distinct non-volatile resistive states, emulating a depressing synapse.Alternating pulse polarity can produce short-term potentiation.
- Memristive switching is rate-dependent and can store and process spiking events locally, while nanoscale dimensions support higher cell density.
- Memristors can be aggressively scaled because their MIM structure places the active operation in the insulating material.Reducing insulator thickness lowers set and read voltages.
- Single devices as small as 10 × 10 nm have been demonstrated, while crossbar arrays organize many addressable synapses compactly.
3. Memristor-based neuro-computing architectures
Memristor-based architectures use dense crossbars as synapses driven by asynchronous spikes, including local STDP learning without global synchronization. These designs support scalable hierarchical and multi-chip event-driven systems.
- Memristors can represent binary potentiated or depressed states or analog synaptic weights in dense crossbar arrays connecting silicon neurons.
- Asynchronous pre- and post-synaptic spike pairs implement STDP without global or local synchronization.Pulse waveforms and thresholded voltage changes can produce arbitrary, including biologically plausible, STDP update functions.
- Pulse shaping can alter the STDP learning function or make it evolve as learning progresses.
- Crossbar arrays can support hierarchical learning networks and multi-chip architectures communicating spikes asynchronously through AER.
- Present-day 40 nm CMOS could fit a neuron within a 10 µm × 10 µm area, enabling dense neuron and synapse integration.The proposed scaling includes about 10^4 synapses per neuron.
- Large systems face spike communication bottlenecks, motivating nearest-neighbor 2D-grid network-on-chip and network-on-board designs.
4. Neuromorphic and hybrid memristor-CMOS synapse circuits
The paper combines dense, low-power memristive weight storage with CMOS circuits that reproduce synaptic biophysics and temporal dynamics. The proposed array provides independent synaptic weights while sharing temporal dynamics across synapses.
- 4.1. A CMOS neuromorphic synapse: The DPI circuit produces biologically plausible linear dynamics and nonlinear short-term plasticity through a translinear loop.Its output current Isyn follows the synaptic impulse response derived from the circuit structure.
- 4.1. A CMOS neuromorphic synapse: A 10 ms time constant requires approximately C = 1 pF when Iτ = 5 pA and UT = 25 mV, enabling compact integration of many silicon synapses.The DPI circuit uses Iw and Ith as local weight and global scaling terms for plasticity mechanisms.
- 4. Neuromorphic and hybrid memristor-CMOS synapse circuits: The hybrid memristor-CMOS circuit combines dense, low-power long-term synaptic-weight storage with detailed synaptic biophysics.Memristors provide storage elements, while CMOS circuitry emulates synaptic behavior.
- 4.2. A new hybrid memristor-CMOS neuromorphic synapse: The proposed array supports N synapses with independent weights and shared temporal dynamics, using one integrating element through time-multiplexing.The shared DPI dynamics reduce silicon area, while each memristor independently modulates synaptic current.
- 4.2. A new hybrid memristor-CMOS neuromorphic synapse: Memristor conductance represents synaptic weight and can model stochastic ion-channel opening when devices approach bistable operation.This behavior is a limitation for precise analog weights but can support compact stochastic synapse emulation.
- 4.2. A new hybrid memristor-CMOS neuromorphic synapse: SPICE simulations evaluate postsynaptic EPSC responses for four memristor conductance values in a 180 nm CMOS implementation.The simulation uses Ithr = 2 pA, Iτ = 10 pA, and Vw = 700 mV.
5. Brain-inspired probabilistic computation
The paper frames variability and stochasticity as properties that biological and artificial systems can exploit for probabilistic computation. It connects these properties to uncertain inference, learning through exploration, and reservoir computing based on collective dynamics rather than precise components.
- 5. Brain-inspired probabilistic computation: Memristor variability and stochasticity are proposed as resources for robust brain-inspired probabilistic computation rather than effects to eliminate.The paper contrasts this strategy with the brain’s operation using noisy and unreliable nanoscale elements.
- 5. Brain-inspired probabilistic computation: Biological synaptic release is stochastic, with cortical release probabilities ranging from less than 1% to 100%, and may serve a computational role.The passage presents stochastic neurotransmitter transmission as potentially more than a molecular constraint.
- 5. Brain-inspired probabilistic computation: Probabilistic inference addresses noisy or incomplete observations by inferring unobserved variables from observed evidence and learned probabilistic relationships.The paper notes that exact probabilistic inference is generally intractable, motivating practical approximation schemes.
- 5. Brain-inspired probabilistic computation: A local spike-driven learning rule resembling cortical STDP can learn probabilistic relationships from observations in a relatively simple model.This links probabilistic model learning with biologically inspired synaptic mechanisms.
- 5. Brain-inspired probabilistic computation: Noise and variability provide exploration mechanisms in reinforcement learning, while reward-based noisy-readout training can require less informative supervision.Reward-based learning can nevertheless be slower than purely supervised training, depending on the task.
- 5. Brain-inspired probabilistic computation: Reservoir computing tolerates component imprecision because functionality depends on collective dynamical behavior, and heterogeneity can benefit performance.The passage also connects heterogeneous predictions with ensemble-learning methods.
6. Discussion and conclusions
Memristors offer compact, low-power synaptic devices, but array integration, variability, and limited state resolution constrain conventional architectures. The proposed hybrid nanoelectronic-CMOS approach directly emulates real synapses to support probabilistic, variability-robust, fault-tolerant computation.
- Memristor arrays face write-voltage offsets that depend on cell position, directly affecting synaptic weight updates and learning.Electrode resistance in large-scale cross-bars produces these position-dependent offsets.
- Process variability in memristor dimensions produces substantial variability in synapse properties.
- The trade-off between desired synaptic weight resolution and memristor size remains unknown, as does the validity of multi-step weight models at aggressive scaling.
- The paper presents a hybrid nanoelectronic-CMOS architecture that directly emulates real-synapse properties and biophysically realistic responses.
- This co-designed approach is intended to support massively parallel brain-inspired computation that is probabilistic, robust to variability, and fault tolerant by design.