Reliable SPICE Simulations of Memristors, Memcapacitors and Meminductors

D. Biolek; M. Di Ventra; Y. V. Pershin

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Reliable SPICE Simulations of Memristors, Memcapacitors and Meminductors

D. Biolek, M. Di Ventra, Y. V. Pershin

arXiv:1307.2717v1Jul 10, 2013physics.comp-phcond-mat.mes-hall

TL;DR

The paper addresses the need for reliable SPICE simulation of memristive, memcapacitive, and meminductive systems. It presents models, implementation codes, and modeling practices, showing that accuracy and convergence depend on device models, numerical limits, and simulator settings.

Problem
SPICE codes and reliability criteria for many memelement models are not consistently available, while hysteresis can magnify simulation imperfections and convergence problems.
Method
The paper develops ideal and non-ideal models for three memelement classes and provides a general SPICE methodology with codes for PSpice, LTspice, and HSPICE.
Results
The presented models provide good results in PSpice and LTspice, while two HSPICE simulations exhibit serious accuracy or convergence problems that can be overcome using HSPICE-RF.
Takeaways & Limitations
The codes and examples are intended to help researchers avoid common simulation pitfalls and build their own reliable memelement simulations.
Takeaways & Limitations
SPICE results can differ substantially from real system behavior or across simulator environments because finite numerical precision and algorithmic operations can introduce errors.

Abstract

from arXiv · show

Memory circuit elements, namely memristive, memcapacitive and meminductive systems, are gaining considerable attention due to their ubiquity and use in diverse areas of science and technology. Their modeling within the most widely used environment, SPICE, is thus critical to make substantial progress in the design and analysis of complex circuits. Here, we present a collection of models of different memory circuit elements and provide a methodology for their accurate and reliable modeling in the SPICE environment. We also provide codes of these models written in the most popular SPICE versions (PSpice, LTspice, HSPICE) for the benefit of the reader. We expect this to be of great value to the growing community of scientists interested in the wide range of applications of memory circuit elements.

I. INTRODUCTION

Memelements can store analog information without power, but their broader use requires SPICE models that are reliable across physically realizable devices and numerical conditions.

Memelements are two-terminal resistive, capacitive, or inductive devices with memory that can store analog information without a power source.
SPICE enables complex-circuit testing before experimental implementation, making reliable memelements simulation important for saving time and resources.
Existing literature does not always provide SPICE code or reliability criteria, limiting the use of popular memelement models.
The paper provides ideal and non-ideal models for memristive, memcapacitive, and meminductive systems, with implementations in PSpice, LTspice, and HSPICE.
The models emphasize physically different memory devices rather than different sophistication levels for describing the same device.
II. METHODOLOGY FOR ACCURATE AND RELIABLE MODELING OF MEMELEMENTS WITH SPICE: Reliable SPICE modeling must address numerical limits, behavioral-model construction, state and port equations, and transient-analysis settings.

3) Models (in)sensitive to numerical errors:

Reliable SPICE models require choosing state and port equations that limit numerical sensitivity, while accounting for finite precision, integration errors, and simulator-specific behavior.

Sources of numerical sensitivity: Model sensitivity arises from circuit dynamics or improper mathematical construction; ideal integrators accumulate errors, while time-domain differentiation amplifies truncation errors.The paper recommends avoiding d/dt behavioral operations by substituting dual integrating formulations.
Window-function sensitivity: For x < 2.776 × 10^-17, one window-function formulation is cut to zero, whereas another remains limited only below x < 2.225 × 10^-308.The first model therefore generates significantly larger errors near the maximum-memristance boundary.
Window-function sensitivity: Window-function models can freeze near boundary states when truncation errors make the state derivative numerically zero, producing random-duration pseudo-fixed states.The resulting errors may remain latent because simulations can run without warnings or error messages.
State-variable selection: Using a native state variable such as charge or flux provides a less error-sensitive differential equation, after which the element parameter is computed from the state.This approach still accumulates integration errors, but less severely than the sensitive boundary-state formulation.
Integrator implementation: SPICE implementations commonly model integration with a 1-Farad grounded capacitor and controlled current source, with an initial condition and a large shunt resistor for a DC path.Extremely high integration capacitances can cause convergence problems, and integrated quantities should have realistic numerical values.
Integrator implementation: Built-in SPICE integration functions can accumulate truncation errors slightly more than conventional integrator models, but smaller step ceilings can provide the same accuracy.This result is reported for the PSpice Cadence v. 16.3 SDT function.
Port and state modeling: Behavioral port models use controlled voltage or current sources, while variable resistance, capacitance, and inductance are represented through state-dependent constitutive equations.Reliable resistor models avoid divisions by small numbers; fixed positive parts can be separated from variable behavioral parts to prevent ideal-source conflicts.

Meminductive systems

Meminductive systems are implemented according to whether flux or current controls the port, with resistor shunts recommended when inductors create convergence or high-frequency problems.

Voltage- or flux-controlled systems: Voltage- or flux-controlled meminductive systems use I = Λ(x, φ, t)φ, implemented with a controlled current source after integrating the port voltage to obtain flux.Here Λ is the inverse meminductance, dependent on state variables and flux.
Current-controlled systems: Current-controlled meminductive systems use φ = L(x, I, t)I, ideally implemented with a controlled flux source or, when unavailable, a voltage source obtained by differentiating flux.The controlled-flux-source option is not commonly available across SPICE-family programs.
Simulator implementations: Micro-Cap, LTspice, and HSPICE provide specialized ways to define inductance or flux as functions of current, supporting more comfortable current-controlled modeling.The available formulation differs by simulator, including inductance formulas, current-dependent flux, or a special current variable.
Convergence measures: Parallel resistors should be added to inductors when convergence problems arise because they limit high-frequency impedance and suppress voltage spikes from abrupt current changes.The resistor should be high enough not to affect circuit parameters and set near the impedance where the inductor quality factor begins to roll off.
Convergence measures: SPICE disallows loops containing only ideal voltage sources and inductors, so such loops must be completed with resistors whose values are low enough but not extremely low.This requirement is another practical boundary on ideal inductive-port implementations.
Related ideal-memory implementation: The ideal memristor model can derive memristance from charge and implement its port with a fixed Roff resistor plus a controlled voltage source.Charge is obtained by integrating port current, with the capacitor-node voltage numerically equal to charge in Coulombs.

B. Model R.2: Bipolar memristive system with threshold

The threshold memristive model represents bipolar switching with bounded memristance and implements its dynamics in SPICE using controlled sources, integrators, threshold functions, and window functions.

Model: The reduced voltage-controlled model uses memristance R as its internal state variable and excludes switching below the voltage threshold.The model is adapted from a threshold-switching approach and defines the device state through R.
Model: The threshold function f(VM) produces switching drive only when the applied voltage exceeds the positive or negative threshold Vt.The parameter β sets the memristance-change rate beyond threshold, while Vt defines the threshold voltage.
Model: The window function confines memristance evolution between Ron and Roff by suppressing state changes at the corresponding boundaries.The step functions in W prevent further change once the memristance reaches either limiting value.
SPICE implementation: SPICE implementation represents the derivative of memristance with controlled-source current, integrates it at node x, and computes port current from terminal voltage divided by memristance.The node voltage is used to represent the integrated memristance, while the memristive port is modeled by a controlled current source.
Results: Positive and negative voltage pulses drive the memristance toward Roff and Ron, while the window function cuts off current at a boundary and thresholds create a stable zone between switching levels.The simulated behavior follows the threshold-driven bipolar switching sequence described for Fig. 5.
Results: 3.1819 kΩ versus 3.1847 kΩ is the reported PSpice low-level memristance and accurate value, respectively, under RELTOL=1u and a maximum timestep of one-thousandth of the simulation time.HSPICE gives an even more accurate computation, and Gear integration is preferred when available because of its stability.

C. Model R.3: Phase change memristive system

The phase-change memristive system models PCM behavior through thermal and phase-state dynamics implemented with SPICE submodels. Simulated voltage pulses reproduce crystallization and amorphization transitions at distinct temperatures.

Model: The PCM model treats temperature T and crystalline fraction Cx as internal state variables in a unipolar second-order memristive system.The model is based on equations describing thermal and phase-change processes.
Model: The model parameters include heat capacitance Ch, dissipation constant δ, ambient temperature Tr, melting point Tm, glass-transition point Tx, and crystallization and amorphization rates α and β.It also specifies threshold-voltage and limiting-memristance parameters for the electrical behavior.
Limitations: The simple PCM model neglects the negative differential-resistance region near threshold voltage Vt, although that region can be incorporated and is not important for the stated read/write voltages.The authors identify this omission as a model limitation rather than as a restriction on the described memory-cell operation.
SPICE implementation: The SPICE implementation uses a resistive-port submodel plus integrator submodels for temperature and crystalline fraction.The temperature and Cx integrators are represented by separate controlled sources, capacitors, and auxiliary resistors.
SPICE implementation: The dissipated power V^2_M/R in the thermal equation can also be computed as the product of voltage and current.This alternative power calculation is shown in the implementation schematic.
Results: 4V/300ns heats the cell to about 339°C and drives crystallization, whereas 6V/100ns raises it to about 739°C and reduces the crystalline fraction close to zero.The first pulse changes Cx from 0 to 1; the second exceeds the melting point and produces amorphization.

D. Model R.4: Insulator-to-metal transition memristive system

This section presents a thermally driven insulator-to-metal memristive model and its SPICE implementation, including a relaxation-oscillator demonstration. The model captures realistic switching behavior but raises numerical concerns near state-variable boundaries.

Model: The model uses the metallic phase fraction u = rmet/rch as the internal state variable for an insulator-to-metal transition device.The metallic and conduction-channel radii define the phase composition state variable.
Model properties: The model describes a unipolar, current-controlled device driven by a thermally induced insulator-to-metal phase transition.The underlying device model can reproduce complex dynamics, including sub-nanosecond switching times.
Limitations: The equations contain logarithms and divisions involving u, which can create numerical difficulties because u varies between 0 and 1.These structural features motivate careful implementation and numerical handling.
Implementation: The SPICE implementation represents the memristive port with a fixed resistor and controlled current source, while a capacitor integrates the state equation.A 10^-12 scaling factor is used to prevent convergence problems from large time derivatives of u.
Results: The PSpice simulation of a Pearson-Anson relaxation oscillator reproduces the outputs originally published for the experimental oscillator.The oxide switch functions as a current-controlled negative differential resistor in the oscillator.

B. Model C.2: Multilayer memcapacitive system

This section develops a two-layer memcapacitive model whose internal tunnel-junction dynamics produce nonpinched charge-voltage hysteresis. Reliable SPICE implementation requires approximations and underflow-aware numerical treatment.

Model: The multilayer system contains two internal metal layers embedded in the dielectric between capacitor plates and is modeled as a charge-controlled memcapacitive system.The two-layer realization is represented by an equivalent circuit containing capacitors and nonlinear resistive behavior.
Implementation: The equivalent circuit uses a controlled current source to model the nonlinear resistor and reproduces the internal-layer voltage and charge relationships.The current I12 determines the charge q − Q associated with the internal layers.
Numerical considerations: The tunnel-junction current I12 spans a range from about 10^-127 to 10^-6 across the stated voltage ratios, exceeding SPICE numerical limits.The low-voltage region eV1 < U produces currents far below SPICE’s numerical threshold.
Numerical considerations: The implementation limits the logarithm of I12 and then reconstructs the current by inverse logarithm to prevent numerical underflow.The supplied SPICE codes can include the second term of the current expression when required.
Results: The SPICE codes reproduce the results from the referenced multilayer study, including a nonpinched charge-voltage hysteresis loop and frequency-dependent hysteresis.The model also supports analysis of diverging and negative capacitance.

C. Model C.3: Bistable membrane memcapacitive system

This section presents a bistable membrane memcapacitive model with two equilibrium states and demonstrates its transient behavior under sinusoidal excitation. The model reproduces frequency-dependent hysteresis and supports pulse-driven and chaotic-dynamics analyses.

Model: The model describes a bistable membrane whose dimensionless displacement and velocity serve as internal state variables.The membrane has equilibrium positions ±z0, with damping, natural frequency, mass, and geometry defining the dimensionless formulation.
Features: The device has two well-defined equilibrium states, making it suited to binary applications.Its bistability follows from the membrane dynamics represented in the model.
Implementation: The memcapacitive port is implemented as two serial capacitors, one fixed at C0 and one dependent on membrane displacement y.A controlled voltage source models the displacement-dependent capacitance, while charge is obtained from capacitor voltage and capacitance.
Results: PSpice transient analysis confirms hysteresis at intermediate frequencies relative to the system’s natural frequency.The same simulations enable analysis under voltage pulses and can show chaotic device behavior under conditions specified in the reference.

D. Model C.4: Bipolar memcapacitive system with threshold

This section presents a generic bipolar memcapacitive model with voltage-threshold switching and bounded memcapacitance. PSpice and LTspice perform well, whereas HSPICE exhibits accuracy and convergence problems for the examined implementations.

Model: The model uses memcapacitance C as its internal state variable and applies threshold-dependent dynamics with a window function.The threshold function governs switching, while the window function confines C between its limiting values.
Model: The threshold voltage Vt and limiting values Clow and Chigh define when memcapacitance changes and the interval in which it remains bounded.The change occurs when |VC| > Vt.
Features: The model combines a widespread physical-device attribute with a structure related to bipolar threshold memristive models.Its stated advantages are a switching threshold and limiting memcapacitance values.
Implementation: The two model realizations compute the state variable by integrating its differential equation, while one formulation avoids differentiating charge.The alternative realization is intended to improve the computational formulation of the memcapacitor current.
Results: PSpice and LTspice provide good results, but HSPICE shows serious accuracy and convergence problems that can be overcome using HSPICE-RF.PSpice results demonstrate periodic switching between Clow and Chigh states.

V. SPICE MODELING OF MEMINDUCTIVE DEVICES

The section develops SPICE models for ideal, effective, and threshold meminductive systems, then demonstrates their simulated hysteresis behavior and simulator-specific reliability. The models represent meminductance through integrated state variables, flux calculations, and controlled sources.

A. Ideal meminductor: Current-controlled meminductors are defined through charge-dependent meminductance, with switching models bounded by Llow and Lhigh.The charge q(t) is the integral of current, and the meminductance can also be expressed from the initial inductance Lini.
A. Ideal meminductor: The ideal meminductor SPICE implementation integrates port current into charge, computes flux from meminductance and current, and differentiates flux to obtain terminal voltage.This implementation uses controlled sources and time-domain integration or differentiation.
A. Ideal meminductor: A 5mA/10Hz sinusoidal drive produces an odd-symmetric flux-current pinched hysteresis loop and high-frequency shrinking in the ideal meminductor simulation.The transient results also show the meminductance-voltage relationship described for the model.
B. Model L.2: Effective meminductive system: The effective meminductive system couples a coil L1 to an LCR contour, with mutual inductance M = k√L1L2 and 0 ≤ k ≤ 1.The circuit does not provide non-volatile information storage and has similarities to elastic memcapacitive systems.
B. Model L.2: Effective meminductive system: A 1mA/100kHz drive makes effective meminductance depend on the ratio of currents in L2 and L1, producing a nonpinched flux-current hysteresis loop.The flux and exciting-current zero crossings differ, explaining why the loop does not pass through the origin.
C. Model L.3: Bipolar meminductive system with threshold: The threshold meminductive model confines meminductance changes between Llow and Lhigh using threshold and window functions.The threshold current It and rate parameter β govern switching once the current magnitude exceeds the threshold.
C. Model L.3: Bipolar meminductive system with threshold: PSpice and LTspice support both equivalent threshold-model implementations, whereas HSPICE supports model (a) and reports convergence problems for model (b).The HSPICE issue can be overcome using HSPICE RF instead of HSPICE.
C. Model L.3: Bipolar meminductive system with threshold: With It = 10µA and a sinusoidal 12µA/50kHz drive, the simulated meminductance initially remains at Linit before switching to Llow above a proper current magnitude.The transient output includes the flux-current pinched hysteresis loop and meminductance waveform.

VI. SETTING THE ANALYSIS PARAMETERS AND SPICE OPTIONS

The section distinguishes convergence from accuracy problems in SPICE transient analysis and introduces the analysis commands and numerical stages that govern both. Reliable simulation requires considering model correctness alongside transient-analysis settings.

Problem types: SPICE analysis problems comprise convergence failures, where no solution is found, and accuracy errors, where a solution is found but modified by numerical error.The section emphasizes that accuracy improvements can promote convergence problems, making highly accurate transient analysis a compromise.
Transient-analysis controls: Transient analysis uses .TRAN syntax with print time and stop time, optionally including start time, maximum step size, and skipbp or uic flags.The available form affects how the transient analysis is initialized and stepped.
Transient-analysis controls: Transient simulation has a DC bias-point stage followed by a timepoint sweep, while .OPTIONS settings affect error criteria and iteration algorithms.The DC stage can be skipped with skipbp, although this is not generally recommended.

Convergence aids for DC bias point computation

The section presents simulator-specific aids for DC and transient convergence, then explains how integration, timestep, and error settings trade accuracy against robustness. It recommends checking model validity and tuning options systematically.

DC bias-point convergence: DC-bias convergence depends on Newton-Raphson iteration and simulator-specific aids, with HSPICE difficulties especially associated with implementations C.4 and L.3.PSpice and LTspice often converge for models built according to the paper’s modeling rules, but convergence also depends on application conditions.
DC bias-point convergence: Recommended DC aids include raising ITL1, supplying .NODESET estimates, invoking source stepping, increasing GMIN, and adjusting RELTOL, VNTOL, and ABSTOL.Several adjustments improve convergence at the expense of accuracy.
Timepoint-sweep convergence: Transient convergence failures arise from the combined action of Newton-Raphson and timestep-control algorithms and may produce “Internal Timestep Too Small” errors.The section recommends checking the model first, then adjusting iteration limits, integration method, error criteria, and TRTOL.
Accuracy limits: Accuracy is limited by numerical representation and noise, and increasing accuracy can worsen convergence problems.The paper identifies these limits as fundamental constraints of transient-analysis tuning.
Accuracy limits: The recommended workflow combines tighter RELTOL, suitable GMIN, integration-method selection, and reduced maximum timestep to control ringing, overshoot, and accumulated errors.GEAR2 can be optimal for memelements, although trapezoidal integration is preferable for some listed systems.
Accuracy control: Tightening RELTOL and TRTOL reduces timestep size under LTE control, with TRTOL refining integration while RELTOL affects both integration and Newton-Raphson precision.The paper reports that LTspice’s default TRTOL yields approximately 2.6 times smaller timesteps than PSpice’s default.
Practical guidance: The paper provides executable model codes and examples across PSpice, LTspice, and HSPICE to support reliable simulation practice.The codes are intended for direct testing and for building further simulations.

APPENDIX A SPICE CODES FOR MODEL R.1

The appendices provide SPICE source-code implementations for memristive models, including ideal, threshold, phase-change, and insulator-to-metal-transition devices. Codes are supplied for PSpice, LTspice, and HSPICE with simulator-specific options and test circuits.

Model R.1: The ideal memristor R1 code implements a resistive port and an integrator model, with PSpice/LTspice and HSPICE variants.The examples include simulator-specific commands and transient-analysis settings.
Model R.2: The bipolar threshold memristive system R2 code defines Ron, Roff, Rinit, β, and Vt parameters and uses a smoothed window function.Separate PSpice/LTspice and HSPICE source-code examples are provided.
Model R.3: The phase-change memristive system R3 code models state evolution through temperature-related parameters, smoothed step functions, and an internal capacitance Cx.The appendices include both PSpice/LTspice and HSPICE implementations with test excitation.
Model R.4: The insulator-to-metal-transition model R4 code defines thermal and geometric parameters and includes a Pearson-Anson relaxation-oscillator test circuit.PSpice/LTspice and HSPICE variants use related but simulator-specific transient-analysis syntax.
Model R.4: The R4 HSPICE example completes the oscillator netlist with transient analysis and probing of internal voltages and currents.The code is explicitly presented as an HSPICE implementation of the insulator-to-metal-transition model.

PSpice and LTspice code

The PSpice and LTspice listings implement ideal, multilayer, bistable-membrane, and threshold memcapacitive systems with corresponding simulation testbenches.

Ideal memcapacitor C1: The ideal memcapacitor model defines capacitance between Clow and Chigh as a function of the integrated state variable phi.The PSpice/LTspice version uses a behavioral C(phi) function, while the HSPICE listing expresses the same relation as a parameterized function.
Multilayer memcapacitive system C2: The multilayer memcapacitive system computes C0, C1, and C2 from dielectric thickness, layer spacing, area, and relative permittivity.The supplied parameters include d=100n, del=66.6n, Su=100u, and er=5.
Bistable membrane memcapacitive system C3: The bistable membrane model uses a fixed base capacitance C0 and behavioral source terms involving the state variables Q and y.The PSpice/LTspice listing sets y0=0.2, yd0=0, gamma=0.7, b=1, and C0=10p.
Bipolar memcapacitive system with threshold C4: The threshold memcapacitor uses Clow, Chigh, Cinit, beta, and Vt parameters with smoothed threshold and window functions.The example sets Clow=1p, Chigh=100p, Cinit=50p, beta=70u, and Vt=3, and simulates a 4 V, 50 kHz sinusoidal drive.

HSPICE code

The HSPICE listings provide implementations and testbenches for ideal and effective meminductive systems, along with threshold meminductive models and transient simulation settings.

Ideal meminductor L1: The ideal HSPICE meminductor defines inductance as a state-dependent function L(q) bounded by Llow and Lhigh.The model integrates current into Q and uses L(V(Q)) in the inductive branch.
Ideal meminductor L1: The ideal meminductor testbench drives the model with a 5 mA, 10 Hz sinusoidal current for a 200 ms transient analysis.The listing uses runlvl=0, lvltim=1, and the Gear method.
Effective meminductive system L2: The effective meminductive system combines two coupled inductors, a resistor, and a capacitor, with k=0.8 defining inductive coupling.The HSPICE model uses L1=L2=1u, R=1, and C=1u, and computes flux by integrating the input voltage.
Bipolar meminductive system with threshold L3: The threshold meminductive model uses low and high inductance bounds, an initial inductance, a gain beta, and a current threshold It.The HSPICE parameters are Llow=1u, Lhigh=100u, Linit=50u, beta=10meg, and It=10u.
Bipolar meminductive system with threshold L3: The threshold meminductor testbench applies a 12 uA, 50 kHz sinusoidal current and performs a 100 us transient simulation.The HSPICE setup uses runlvl=6, KCLTEST, delmax=1n, and a 0.1u transient step.