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Large-Scale MIMO Detection for 3GPP LTE: Algorithms and FPGA Implementations

Michael Wu, Bei Yin, Guohui Wang, Chris Dick, Joseph R. Cavallaro, Christoph Studer

arXiv:1403.5711v1cs.IT

TL;DR

Large-scale MIMO detection in SC-FDMA LTE uplinks faces high matrix-inversion complexity as antenna and user counts grow. The paper proposes Neumann-series approximate inversion alongside exact Cholesky-based detection, analyzes their error and implementation trade-offs, and demonstrates FPGA designs exceeding 600 Mb/s for a 128-antenna, 8-user system.

  • Problem

    SC-FDMA-based large-scale MIMO uplink detection becomes computationally demanding because large antenna and user dimensions make matrix inversion costly.

  • Method

    The paper combines linear soft-output detection with a Neumann-series approximate matrix inversion and compares it with exact Cholesky-based inversion through error analysis and FPGA implementations.

  • Results

    603 Mb/s is achieved for the 128×8 system, while the approximate detector uses 19% fewer LUT slices and 26% fewer DSP48 units than the Cholesky-based unit for 128×8, K = 3.

  • Takeaways & Limitations

    Detector choice depends on the ratio between base-station antennas and users and the desired error-rate performance, with approximation offering lower complexity at large antenna ratios.

Abstract

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Large-scale (or massive) multiple-input multiple-output (MIMO) is expected to be one of the key technologies in next-generation multi-user cellular systems, based on the upcoming 3GPP LTE Release 12 standard, for example. In this work, we propose - to the best of our knowledge - the first VLSI design enabling high-throughput data detection in single-carrier frequency-division multiple access (SC-FDMA)-based large-scale MIMO systems. We propose a new approximate matrix inversion algorithm relying on a Neumann series expansion, which substantially reduces the complexity of linear data detection. We analyze the associated error, and we compare its performance and complexity to those of an exact linear detector. We present corresponding VLSI architectures, which perform exact and approximate soft-output detection for large-scale MIMO systems with various antenna/user configurations. Reference implementation results for a Xilinx Virtex-7 XC7VX980T FPGA show that our designs are able to achieve more than 600 Mb/s for a 128 antenna, 8 user 3GPP LTE-based large-scale MIMO system. We finally provide a performance/complexity trade-off comparison using the presented FPGA designs, which reveals that the detector circuit of choice is determined by the ratio between BS antennas and users, as well as the desired error-rate performance.

I. INTRODUCTION

Large-scale MIMO increases base-station antennas and simultaneously serves many users, improving communication capabilities while making SC-FDMA uplink detection substantially more complex. This paper addresses that complexity with approximate and exact linear soft-output detectors and corresponding VLSI/FPGA implementations.

  • A. Blessing and Curse of Massive MIMO: Large-scale MIMO uses many more base-station antennas than conventional systems while serving multiple users in the same frequency band.It promises improvements in spectral efficiency, link reliability, and coverage.
  • A. Blessing and Curse of Massive MIMO: The resulting uplink detection complexity and power consumption increase by orders of magnitude, with SC-FDMA further increasing problem dimensionality.The challenge is especially acute when hundreds of base-station antennas and many users are present.
  • B. Contributions: The paper targets SC-FDMA-based large-scale MIMO uplink detection using linear soft-output detection and a Neumann-series approximate matrix inversion method.The work analyzes implementation trade-offs between approximate and exact linear detection.
  • B. Contributions: Approximation error depends on the ratio between base-station antennas and users, favoring approximation at medium-to-large ratios and exact detection at small ratios.The paper presents FPGA designs for both approaches across multiple antenna configurations.
  • A. LTE Uplink Model: The designs support SC-FDMA transmission by transforming user symbols between time and frequency domains and modeling received signals as y = Hs+n.The system includes DFT/IDFT processing, a cyclic prefix, and simultaneous transmission from all users.

B. Linear MMSE Detection

Linear MMSE detection equalizes received SC-FDMA symbols per subcarrier and then produces soft bit information from time-domain estimates. Its main computational burden is the explicit inversion of a regularized user-dimensional Gram matrix.

  • Assumption: The paper assumes perfect channel-state information throughout and leaves the impact of imperfect CSI on error-rate performance for future work.This assumption applies to the channel information used by the detector.
  • Linear MMSE Detection: Linear SC-FDMA detection first performs channel equalization and then computes soft-output LLRs from the equalized symbols.The equalized frequency-domain symbols are transformed to the time domain before LLR extraction.
  • Channel equalization: The MMSE detector models each subcarrier as y_w = H_ws_w + n_w and computes equalized symbols using a per-subcarrier MMSE equalization matrix.The channel gains and received symbols are indexed by subcarrier, antenna, and user.
  • Channel equalization: The conventional implementation forms the matched-filter output and regularized Gram matrix before explicitly computing the U × U inverse A_w^-1.This inverse is required for the equalized symbols and for post-equalization SINR calculations used in soft-output detection.
  • LLR computation: After IDFT processing, symbol estimates are modeled as independent Gaussian variables to compute max-log LLRs using effective channel gain and post-equalization noise-plus-interference variance.The detector associates each estimate with an effective gain, NPI variance, SINR, and constellation subsets for each bit.

III. APPROXIMATE MMSE DETECTION VIA NEUMANN SERIES EXPANSION

Large-scale MIMO makes exact matrix inversion costly when many users are served, motivating low-complexity alternatives for LTE uplink detection. The next approach addresses this burden with an approximate inversion method.

  • III. Approximate MMSE Detection via Neumann Series Expansion: Explicit inversion of the U × U matrix A_w can quickly become excessively complex as the number of users increases in large-scale MIMO.Small-scale LTE designs can compute exact inverses explicitly, but that approach is unsuitable for larger user dimensions.
  • III. Approximate MMSE Detection via Neumann Series Expansion: Practical SC-FDMA-based large-scale MIMO detection therefore requires low-complexity matrix inversion methods.The paper introduces an approximate solution after identifying explicit inversion as the main computational bottleneck.

A. Neumann Series Approximation

The paper exploits diagonal dominance in large-scale MIMO Gram matrices to approximate matrix inverses with a truncated Neumann series, reducing complexity while retaining accuracy. The approximation uses the diagonal matrix as a starting point and keeps only a few series terms, but higher orders can erase the complexity advantage.

  • Approximation principle: When U ≪ B, large-scale MIMO Gram matrices become diagonally dominant, motivating approximation of A_w by its main diagonal D_w.For i.i.d. Gaussian channels in the large-antenna limit, G_w approaches I_U.
  • Approximation principle: A crude diagonal approximation has much lower complexity than exact inversion but can cause significant performance loss for realistic antenna/user configurations.The Neumann expansion is introduced to improve accuracy without returning to full inversion complexity.
  • Neumann expansion: The method decomposes A_w into D_w + E_w and substitutes D_w for the expansion matrix, with convergence guaranteed when lim n→∞(−D_w^-1E_w)^n = 0_U×U.D_w is the main diagonal, while E_w is the hollow regularized Gram matrix.
  • Neumann expansion: The proposed approximate inverse retains only the first K terms of the Neumann series, enabling low-complexity computation when K is small.The resulting approximation is used to form an approximate MMSE equalization matrix.
  • Complexity: For K = 2, the approximation scales with O(U^2), compared with O(U^3) for exact inversion.For K = 1, the approximation coincides with the MF detector.
  • Complexity: For K ≥ 4, exact inversion can have lower complexity than the proposed approximation, although K = 3 still requires fewer arithmetic operations than explicit inversion.At K = 3, complexity scales with O(U^3), equivalent to exact inversion asymptotically.

B. Analysis of the Approximation Error

The paper bounds the error of Neumann-series approximate inversion for MMSE detection and derives conditions under which convergence and small residual error are likely. It also develops low-complexity approximations for the post-equalization variance and effective channel gain.

  • The residual approximation error approaches zero exponentially fast as K increases when the stated convergence condition is satisfied.
  • Increasing the BS-antenna-to-user ratio raises the probability that the Neumann series converges and that the residual estimation error is small.
  • As B approaches infinity with U fixed, convergence occurs with probability 1 for α ∈ (0, 1], and the K-term approximation error becomes arbitrarily small.
  • The analytical condition also applies to ZF detection but is considered pessimistic and likely sub-optimal when the regularization term is nonzero.
  • The approximate inverse replaces the exact inverse in soft-output detection, requiring an alternative post-equalization NPI variance expression.
  • The proposed low-complexity NPI variance approximation uses the K = 1 term and requires only L inner products of U operations each.
  • For U = 4, B = 8, and K = 3, the low-complexity NPI approximation loses less than 0.02 dB at a BLER of 10^-2 versus exact NPI computation.

D. Simulation Results

The paper evaluates approximate and exact detection using practically relevant large-scale MIMO antenna configurations. It references prototypes with 64 and 96 BS antennas when motivating the simulation settings.

  • The Samsung Full-Dimensional MIMO prototype has 64 BS antennas, while Rice University's massive MIMO platform has 96 BS antennas.

1) Computational complexity:

The Neumann-series approximation reduces multiplication complexity relative to exact Cholesky-based inversion for K ≤3, while its error-rate suitability depends on the antenna-to-user ratio and modulation.

  • Complexity comparison: For K ≥3, a K-term approximation has complexity O((K −2)U 3), giving O(U 3) for K = 3.The K = 3 scaling matches that of an exact Cholesky-based inverse, although operation counts can differ substantially.
  • Complexity comparison: For K ≤3, the Neumann-series approach requires substantially fewer real-valued multiplications than exact Cholesky-based inversion.The comparison counts real-valued multiplications across varying user counts U.
  • Error-rate performance: For small BS-antenna-to-user ratios, MF and K = 2 produce large residual errors.The MF detector is equivalent to K = 1 in this comparison.
  • Error-rate performance: Under the 10% BLER requirement, MF and K = 2 are unsuitable for the considered 64-QAM cases, while larger antenna counts can partially recover the error floor.Simulations report MF below 10^-2 BLER for U = 4 and B = 512.
  • Error-rate performance: For 64-QAM, K = 3 approaches exact-detector performance with less than 0.25 dB SNR loss at 10^-2 BLER in specified configurations.The stated configurations are K = 3, U = 4 cases and K = 3, U = 8, B = 256.
  • Design choice: Systems with small antenna ratios require exact inversion, whereas systems with large ratios can use the approximate inverse.The choice is tied to the associated error-rate and complexity trade-off.

IV. VLSI ARCHITECTURE

The proposed detector architecture combines preprocessing, subcarrier processing, buffering, IFFT, and soft-output LLR computation, with a configurable Neumann-series inversion path alongside an exact reference path.

  • Architecture overview: Two VLSI designs implement approximate and exact matrix inversion for a direct hardware complexity versus error-rate comparison.The approximate design uses the proposed inversion approach; the exact design uses an exact inverse.
  • Architecture overview: The general engine includes matched filtering, regularized Gram-matrix formation, approximate inversion, equalization, SINR computation, buffering, IFFT, and LLR computation.Multiple preprocessing instances support changing channel estimates across subcarriers and SC-FDMA symbols.
  • Approximate inversion unit: The approximate inversion unit uses one systolic array to compute the regularized Gram matrix and inverse across four phases.The number of Neumann-series terms is selectable at run time.
  • Approximate inversion unit: Normalization scales the regularized Gram matrix so diagonal entries are close to 1, mitigating dynamic-range issues in fixed-point inversion circuits.The matrix is diagonally dominant with diagonal entries close to B.
  • Architecture overview: Channel estimates that change slowly need not trigger inversion for every SC-FDMA symbol, enabling reduced power consumption or increased throughput.This is presented as an exploitable practical operating condition.
  • Approximate inversion unit: The systolic array computes D−1B using reciprocal and scalar operations, then forms higher-order Neumann terms through matrix multiplication.The K-term result can be iterated for a configurable number of terms and stored in distributed register files.

2) Matched filter computation:

The matched-filter and equalization paths use linear arrays of MAC-based processing elements, while SINR computation derives effective gains and noise-plus-interference quantities for soft detection.

  • Matched filter computation: The matched-filter unit uses U processing elements, each containing one MAC and a scaling unit.Each PE corresponds to one row of the Hermitian channel-product matrix.
  • Matched filter computation: The matched-filter unit reads one received-vector entry per clock cycle, accumulates products, and normalizes the final output by 1/B.The result is the normalized matched-filter output.
  • Equalization: The equalization unit uses U MAC units to multiply columns of the normalized approximate inverse by matched-filter outputs.It produces one equalized symbol every U clock cycles.
  • SINR computation: The SINR unit computes approximate effective channel gains and the approximate noise-plus-interference quantity using MAC units.It also computes reciprocals of the effective gains for subsequent LLR computation.

D. IFFT and LLR Computation Units

The design converts equalized subcarrier symbols to the user domain with an IFFT and generates max-log LLRs, while the exact reference path uses Cholesky decomposition and forward/backward substitution.

  • D. IFFT and LLR Computation Units: For a 1200-subcarrier IFFT, the Xilinx core processes a new data set every 3779 clock cycles.The implementation uses the core’s IDFT capability for SC-FDMA processing.
  • D. IFFT and LLR Computation Units: The LLR unit generates max-log soft outputs from effective channel gains and post-equalization SINR values.It exploits LTE Gray mappings for BPSK, QPSK, 16-QAM, and 64-QAM.
  • D. IFFT and LLR Computation Units: The LLR computation scales equalized time-domain symbols by reciprocal effective gains, evaluates piecewise-linear functions, and scales them by post-equalization SINR.Logical shifts and additions implement the piecewise-linear functions, and lookup tables provide reciprocals.
  • D. IFFT and LLR Computation Units: A single LLR-unit instance processes one symbol per clock cycle, reaching 1.89 Gb/s for 64-QAM at 317 MHz.The throughput figure applies to the resulting LLR computation unit.
  • Exact inversion reference: The exact reference path forms the regularized Gram matrix, performs Cholesky decomposition, and computes the inverse through forward and backward substitution.The substitution procedure avoids a costly direct matrix-by-matrix multiplication.
  • Exact inversion reference: The exact-inversion architecture separates Gram-matrix computation, inversion, and forward/backward substitution into pipeline stages.The forward/backward unit reuses symmetric substitution hardware and uses U processor elements in parallel.
  • Exact inversion reference: For an input matrix of dimension U, the forward substitution unit uses U 2 complex-valued multipliers and the full unit uses 2U 2.The architecture solves the independent substitution systems in parallel.

V. IMPLEMENTATION RESULTS AND TRADE-OFFS

The FPGA implementations support high-throughput LTE-A large-scale MIMO detection, while exposing trade-offs between fixed-point precision, hardware complexity, error-rate performance, and antenna-to-user ratio.

  • A. Fixed-Point Design Parameters: The fixed-point implementation is virtually indistinguishable from floating-point performance, with less than 0.05 dB SNR loss at 10% BLER.
  • B. FPGA Implementation Results: All designs run at 317 MHz and achieve 603 Mb/s for 128×8 and 301 Mb/s for 64×4 systems.The 64×4 design meets the 300 Mb/s LTE-A peak-rate requirement for four users in 20 MHz bandwidth.
  • B. FPGA Implementation Results: For 64×4, K = 3 uses 56% fewer LUT slices and 29% fewer DSP48 units than the Cholesky-based detector.
  • B. FPGA Implementation Results: For 128×8, K = 3 uses 19% fewer LUT slices and 26% fewer DSP48 units than the Cholesky-based detector.Hardware savings become significantly larger as the number of users increases.
  • C. Performance/Complexity Trade-off: The antenna-to-user ratio determines whether approximate or exact inversion is more beneficial in practical large-scale MIMO systems.For large B/U ratios, K = 3 has similar SNR performance to exact inversion; for small ratios, the performance gap is larger.
  • C. Performance/Complexity Trade-off: Comparison with prior small-scale MIMO FPGA detectors is difficult because those designs use different algorithms and were not implemented on the same Virtex-7 FPGA.The paper therefore compares against its own Cholesky-based reference circuit.
  • VI. CONCLUSIONS: Future work includes iterative detection and decoding and low-complexity near-optimal detection for large-dimensional SC-FDMA systems.

APPENDIX A PROOF OF THEOREM 1

The appendix proves Theorem 1 through lemmas bounding moments and matrix-error terms under i.i.d. Gaussian channel assumptions, followed by Markov’s inequality.

  • The proof assumes i.i.d. circularly symmetric complex Gaussian variables with unit variance in its moment calculations.
  • Lemma 3 models 2g^-1 as an inverse chi-square random variable with 2B degrees of freedom and uses its fourth moment.
  • The regularized Gram matrix is decomposed into its diagonal component and error component before bounding the matrix approximation terms.
  • The proof applies the lemma bounds to expected values and then uses Markov’s inequality to obtain the final theorem bound.
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