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Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array
Sukru Burc Eryilmaz, Duygu Kuzum, Rakesh Jeyasingh, SangBum Kim, Matthew BrightSky, Chung Lam, H. -S. Philip Wong
TL;DR
Existing experimental work had demonstrated nanoscale synaptic devices mainly at the single-device level, leaving network-level associative learning limited. This paper experimentally implements Hebbian learning in a grid-connected PCM synaptic array, demonstrating associative pattern recall while examining variation tolerance and energy tradeoffs.
Problem
Experimental demonstrations of nanoscale synaptic devices had largely remained at the single-device level, with network-level studies limited to simulations.
Method
The study implements a fully connected recurrent Hopfield network using PCM synaptic devices and Hebbian updates in a crossbar array.
Results
The hardware network stored presented patterns and recalled missing pixels associatively, with increased training epochs accommodating larger initial resistance variations.
Takeaways & Limitations
The demonstrated small-scale synaptic array supports robust brain-inspired learning, while variation tolerance trades off against synaptic-device energy consumption.
Takeaways & Limitations
Read-voltage variation in integrated CMOS neurons can change the number of training epochs required, and the threshold scheme assumes four pixels are ON during recall.
Abstract
from arXiv · showhide
Recent advances in neuroscience together with nanoscale electronic device technology have resulted in huge interests in realizing brain-like computing hardwares using emerging nanoscale memory devices as synaptic elements. Although there has been experimental work that demonstrated the operation of nanoscale synaptic element at the single device level, network level studies have been limited to simulations. In this work, we demonstrate, using experiments, array level associative learning using phase change synaptic devices connected in a grid like configuration similar to the organization of the biological brain. Implementing Hebbian learning with phase change memory cells, the synaptic grid was able to store presented patterns and recall missing patterns in an associative brain-like fashion. We found that the system is robust to device variations, and large variations in cell resistance states can be accommodated by increasing the number of training epochs. We illustrated the tradeoff between variation tolerance of the network and the overall energy consumption, and found that energy consumption is decreased significantly for lower variation tolerance.
1. Introduction
CMOS scaling faces physical and economic limits, while device variations and leakage increase challenges for conventional deterministic architectures. Brain-inspired hardware offers a route toward compact, parallel, robust, and energy-efficient information processing using nanoscale synaptic devices.
- 1. Introduction: CMOS scaling is approaching physical and economic limits, while device-to-device and cycle-to-cycle variations increase as devices shrink.Conventional digital architectures require costly extra circuitry to mitigate these variations.
- 1. Introduction: Brain-inspired computing draws on the brain’s massive parallelism, robustness, error tolerance, and energy efficiency.Such systems are suited to pattern recognition involving large amounts of imprecise environmental input.
- 1. Introduction: Hardware implementations aim to realize brain-like parallelism more efficiently than software algorithms running on conventional architectures.Synaptic devices are especially important because networks typically contain many more synapses than neurons.
- 1. Introduction: PCM is a candidate synaptic device because it supports intermediate resistance states through gradual programming.Its conductance levels can emulate changes in synaptic strength, while crossbar connectivity resembles brain-fiber organization.
2. Phase Change Memory Cell Array for Synaptic Operation
The experiments use a 10-by-10 crossbar array of mushroom-type PCM cells as synaptic elements. Gradual resistance programming provides synaptic weight changes, while device-level variation is tolerated without write-and-verify programming.
- Array structure: The experimental array contains 100 mushroom-type PCM cells connected in a crossbar, with each cell selected by a unique wordline–bitline pair.The heater, bottom electrode, phase-change material, and top electrode are vertically stacked.
- Array structure: Each memory cell is accessed by applying appropriate biases to its corresponding wordline and bitline while grounding the substrate and common-source terminals.
- Array structure: The array schematic and microscope image establish the physical organization used for the synaptic experiments.
- Synaptic programming: A long current pulse crystallizes the phase-change material through Joule heating, and pulse amplitude controls gradual SET resistance reduction.The pulses range from a few hundred nanoseconds to a few microseconds.
- Synaptic programming: Resistance variability in PCM cells means gradual programming does not require every cell to reach an accurately verified resistance level.The paper states that massively parallel brain-like architectures can tolerate such variations.
- Device characterization: Electrical characterization measures single-cell DC switching and alternating SET and RESET cycles, with switching observed at 2 µA.
3. Array Level Learning
A 100-device recurrent Hopfield network uses computer-controlled integrate-and-fire neurons and PCM cells as synapses to learn and recall pixel patterns. Training strengthens connections between ON neurons, enabling missing-pixel recall after 11 epochs, while threshold choice trades recall accuracy against training effort under variation.
- Network architecture: The fully connected recurrent Hopfield network contains 100 synaptic devices and 10 recurrently connected neurons, with each neuron serving as both input and output.Integrate-and-fire neurons are implemented by computer control, while memory cells serve as synapses.
- Neuron model: The experiment treats input current as membrane potential because the neuron model omits membrane capacitance, delays, and timing properties.The paper therefore uses the terms input current and membrane voltage interchangeably.
- Recall operation: During recall, input current through a non-firing neuron is computed from firing-neuron synapses, their resistances, and a 0.1 V read voltage.
- Recall operation: A missing pixel is an ON pixel omitted from the recall input, and a neuron fires when its input current exceeds threshold, completing the recalled pattern.
- Learning results: After 11 epochs, synapses between ON neurons strengthen through resistance decreases, allowing the trained patterns to be recalled.Synaptic weights are tracked as resistance normalized to each device’s initial RESET resistance.
- Variation and tradeoffs: Lowering the threshold can reduce the number of epochs but may cause an incorrect pixel to fire because of device variations.
4. Effect of Variation on Learning Performance
Initial resistance variation affects associative recall: larger variation requires more training epochs, while reduced variation separates potentiated from unchanged synapses more clearly and lowers energy use. The firing threshold is tuned to prevent false firing while enabling missing-pixel recall.
- Threshold selection: The firing threshold is selected to prevent wrong pixels from firing while allowing the missing pixel to fire during recall.It must be high enough to suppress false firing but low enough to preserve recall with minimal energy.
- Resistance evolution: As initial variation decreases, potentiated synapses become more distinguishable from unchanged synapses after the same number of training epochs.Training drives synapses between coactive neurons toward lower resistance values, making their separation more pronounced as variation falls.
- Recall versus variation: 11 epochs were required to recall the missing pixel with 60% initial variation, compared with 1 epoch at 9% variation.The corresponding cases also included 9 epochs at 40% variation and 5 epochs at 24% variation.
- Energy tradeoff: Larger initial variation increases the required training epochs and energy consumption because a larger firing threshold is needed.The threshold adjustment raises the maximum tolerated input condition and extends training.
- Integration boundary: Read-voltage variation may alter the number of training epochs when the grid is integrated with CMOS neurons.The experiments themselves had negligible read-voltage variation, but CMOS integration is expected to introduce it.
- Energy tradeoff: 4.8 nJ was consumed for 9% initial resistance variation, versus 52.8 nJ for 60% variation.These values cover synaptic-device energy during training and recall for pattern 1, excluding wires and neurons.
5. Conclusion
The experiments demonstrate brain-like associative learning in a crossbar array of phase-change synaptic devices. Hebbian plasticity enabled pattern storage and missing-pattern recall, while additional epochs improved variation tolerance at higher energy cost.
- Conclusion: A crossbar array of phase-change synaptic devices demonstrated brain-like associative learning in hardware.The network stored and recalled patterns through Hebbian plasticity.
- Conclusion: Increasing training epochs improved tolerance to initial resistance variations but increased energy consumption.This establishes a tradeoff between robustness and energy use in the demonstrated synaptic array.
6. Methods
Experiments used a probed memory-cell array connected through a switch matrix to semiconductor-analysis and pulse-generation equipment, all controlled by LabVIEW.
- A 25×1 probe card contacted 10 bitlines, 10 wordlines, a common source, a substrate terminal, and three floating terminals.
- The switch matrix connected the array to an Agilent 4156C for DC measurements and an Agilent 81110 for pulse measurements.
- Measurements applied alternating SET and RESET pulses, while gradual SET characterization used one RESET pulse followed by nine gradual SET pulses.
- The measurement setup was computer-controlled through a switch matrix linking the probe card to the memory chip pads.