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Massive MIMO with Non-Ideal Arbitrary Arrays: Hardware Scaling Laws and Circuit-Aware Design

Emil Björnson, Michail Matthaiou, Mérouane Debbah

arXiv:1409.0875v3cs.ITmath.IT

TL;DR

Massive MIMO's circuit power consumption grows with array size, motivating the question of whether hardware imperfections can be tolerated without losing high rates. The paper analyzes an uplink system with multiple imperfections and derives rate expressions and scaling results. Its analysis finds that distortion and noise amplification vanish asymptotically, while phase-drifts remain but are not exacerbated.

  • Problem

    Although uplink and downlink transmit powers can decrease as N grows, increasing circuit power consumption can undermine overall energy efficiency.

    Source: §I · p. 1

  • Method

    The paper derives a hardware-aware LMMSE channel estimator and achievable uplink rates with maximum ratio combining for a system with several hardware imperfections.

    Source: §I · p. 2, §VI · p. 12

  • Results

    As N → ∞, only phase-drifts limit achievable rates; additive distortion noise and noise amplification vanish, while phase-drifts are not exacerbated.

    Source: §I · p. 2, §VI · p. 12

  • Takeaways & Limitations

    Numerical results show substantial performance benefits from separate oscillators at each antenna branch rather than a common oscillator.

    Source: §VI · p. 12

    For downlink maximum ratio transmission, similar rate expressions and scaling laws are expected, but their analytic derivation and interpretation are outside the paper's scope.

    Source: §VI · p. 12

Abstract

from arXiv · show

Massive multiple-input multiple-output (MIMO) systems are cellular networks where the base stations (BSs) are equipped with unconventionally many antennas, deployed on co-located or distributed arrays. Huge spatial degrees-of-freedom are achieved by coherent processing over these massive arrays, which provide strong signal gains, resilience to imperfect channel knowledge, and low interference. This comes at the price of more infrastructure; the hardware cost and circuit power consumption scale linearly/affinely with the number of BS antennas $N$. Hence, the key to cost-efficient deployment of large arrays is low-cost antenna branches with low circuit power, in contrast to today's conventional expensive and power-hungry BS antenna branches. Such low-cost transceivers are prone to hardware imperfections, but it has been conjectured that the huge degrees-of-freedom would bring robustness to such imperfections. We prove this claim for a generalized uplink system with multiplicative phase-drifts, additive distortion noise, and noise amplification. Specifically, we derive closed-form expressions for the user rates and a scaling law that shows how fast the hardware imperfections can increase with $N$ while maintaining high rates. The connection between this scaling law and the power consumption of different transceiver circuits is rigorously exemplified. This reveals that one can make the circuit power increase as $\sqrt{N}$, instead of linearly, by careful circuit-aware system design.

I. INTRODUCTION

Massive MIMO offers large spatial degrees of freedom, but the cost and power of its antenna branches grow with array size. This paper models several receiver hardware imperfections jointly and analyzes their effects on channel estimation, achievable rates, and hardware scaling.

I. INTRODUCTION

  • Massive MIMO's spatial degrees of freedom support coherent gains and resilience to imperfect channel knowledge, but antenna-branch costs and circuit power grow with N.The paper frames hardware imperfections as a key concern because relaxing hardware accuracy could enable less expensive, lower-power branches.Source: §I · pp. 1–2

II. SYSTEM MODEL WITH HARDWARE IMPERFECTIONS

  • The model jointly represents multiplicative phase-drifts, signal-proportional distortion noise, amplified receiver noise, and inter-carrier interference across co-located or distributed arrays.Its parameters are δ, κ, and ξ; setting ξ = σ^2 and δ = κ = 0 recovers the conventional model.Source: §I · p. 2, §II · pp. 3–4

I. INTRODUCTION

  • The paper derives a hardware-aware LMMSE channel estimator and closed-form achievable uplink rates with maximum ratio combining, then proves that distortion noise and noise amplification vanish asymptotically while phase-drifts remain but are not exacerbated.The estimator accounts for hardware imperfections and predicts detrimental phase-drift effects.Source: §I · p. 2
  • The scaling law gives sufficient conditions for increasing hardware-imperfection levels with N while maintaining high user rates, and its implications are illustrated for ADCs, LNAs, and LOs.The circuit examples connect hardware cost, imperfection levels, and circuit power consumption.Source: §I · p. 2

II. SYSTEM MODEL WITH HARDWARE IMPERFECTIONS

  • The channel is modeled as Rayleigh block fading with independent user channels and diagonal covariance matrices, an assumption stated to hold with sufficiently separated antennas and rich multipath.The analysis also permits arbitrary non-diagonal covariance matrices, at the cost of more complicated notation and expressions.Source: §II · p. 3

III. PERFORMANCE ANALYSIS

Each coherence block is divided into uplink pilots and data, with pilot placement varying across the block. At least K pilot uses are required to spatially separate the K users in a cell.

III. PERFORMANCE ANALYSIS

  • Each coherence block allocates B ≥ K channel uses to pilots and the remaining T − B uses to uplink data.The pilot-length requirement is stated for spatially separating users within a cell.Source: §III · p. 4
  • Pilot symbols may be placed at the beginning, middle, or uniformly throughout the coherence block, or distributed using a combination of these approaches.Pilot-use indices are denoted τ1, …, τB, and the remaining indices form the data set D.Source: §III · p. 4
  • The transmission protocol distinguishes pilot and data time indices within the T channel uses of each coherence block.The data indices are D = {1, …, T} \ {τ1, …, τB}.Source: §III · p. 4

A. Channel Estimation under Hardware Imperfections

The section develops a new LMMSE channel estimator for pilots affected by phase-drifts and channel-dependent distortion noise. It supports flexible pilot sequences and produces estimates for each data-use time, whether that requires prediction, interpolation, or retrospection.

A. Channel Estimation under Hardware Imperfections

  • Pilot sequences can be selected arbitrarily under power constraints, while within-cell orthogonality is reasonable to avoid intra-cell interference.Network-wide pilot orthogonality requires B ≥ LK, typically much larger than coherence-block length T, so practical designs balance orthogonality against inter-cell interference.Source: A. Channel Estimation under Hardware… · p. 4
  • A new LMMSE estimator is derived because phase-drifts corrupt pilots and distortion noise depends statistically on the channels.Conventional multi-antenna estimators cannot be applied to this generalized model.Source: A. Channel Estimation under Hardware… · p. 4
  • The section gives the corresponding error covariance and defines mean-squared error as the trace of that covariance matrix.Pilot symbols may be distributed at the block beginning, middle, uniformly, or as a preamble plus distributed symbols.Source: Figure 2 · p. 4, A. Channel Estimation under Hardware… · p. 5
  • The estimator provides a channel estimate at each data-use time, handling prediction, interpolation, or retrospection according to pilot placement.The same estimator is used for independent and correlated phase-drifts, though nonlinear estimators may better exploit drift correlations.Source: Figure 2 · p. 4, A. Channel Estimation under Hardware… · p. 5

B. Achievable UE Rates under Hardware Imperfections

The section derives achievable uplink user-rate expressions under imperfect channel knowledge and hardware impairments. It provides closed-form expectations for MRC and explains how oscillator architecture affects interference and rates.

B. Achievable UE Rates under Hardware Imperfections

  • Closed-form expressions for the SINR expectations are derived for MRC, yielding achievable UE rates when substituted into the rate expression.The achievable-rate expressions are lower bounds chosen to guarantee performance despite imperfect channel knowledge and hardware imperfections.Source: B. Achievable UE Rates under Hardware… · p. 5
  • Most terms in the MRC expressions scale linearly with N, while a few scale as N^2 and dominate the asymptotic analysis.Each trace expression or sum over antennas contributes a scaling factor of N.Source: B. Achievable UE Rates under Hardware… · pp. 5–6
  • CLO and SLO cases have the same desired-signal quality but different interference terms; the case with the smaller interference variance gives the larger UE rate.The difference between their second-order moments grows with phase-drift variance; SLO phase terms decay over time, whereas the corresponding CLO term is time-invariant.Source: B. Achievable UE Rates under Hardware… · p. 6
  • With a CLO, phase-drifts leave interference power unchanged, whereas independent SLO rotations make combining components add incoherently and reduce average interference.The SLO benefit is an interference effect, not a change in desired-signal quality.Source: B. Achievable UE Rates under Hardware… · p. 6
  • Separate LOs are expected to provide larger UE rates than a common LO because independent phase-drifts reduce interference over time, at the cost of N LOs.Simulations validate this observation.Source: B. Achievable UE Rates under Hardware… · p. 6

C. Asymptotic Analysis and Hardware Scaling Laws

The asymptotic analysis shows that hardware imperfections need not prevent nonzero limiting rates as arrays grow, and derives conditions for tolerating increasing imperfections. The scaling law distinguishes additive impairments from phase-drift effects and supports circuit-quality tradeoffs.

C. Asymptotic Analysis and Hardware Scaling Laws

  • With MRC and the stated covariance factorization, distortion and receiver noise vanish as N grows, while phase-drifts remain but have no dramatic impact on the asymptotic SINR.The analysis assumes antennas are distributed over spatially separated subarrays, with channel covariance matrices factorized by subarray.Source: C. Asymptotic Analysis and Hardware… · pp. 6–7
  • Temporal pilot orthogonality avoids intra-cell pilot contamination from phase-drift-broken spatial orthogonality, but uses K times less pilot energy per UE.The simulations indicate temporal pilots are beneficial only for extremely large arrays; inter-cell pilot contamination generally cannot be removed because the network has at most B ≤ T orthogonal sequences.Source: C. Asymptotic Analysis and Hardware… · p. 7
  • All SINRs converge to nonzero limits under Corollary 4's hardware scaling conditions, even as the hardware imperfection parameters increase with N.The scaling replaces κ² and ξ by values proportional to N^z1 and N^z2, and δ by a term growing logarithmically with N.Source: C. Asymptotic Analysis and Hardware… · p. 7
  • The scaling law supports relaxing hardware-quality constraints as N increases, potentially lowering circuit energy use or hardware cost while accommodating multiplicative phase-drifts, receiver noise, and inter-carrier interference.It extends an earlier proof based only on additive distortion noise to the broader modeled impairment set.Source: C. Asymptotic Analysis and Hardware… · p. 7
  • For SLOs, the scaling condition captures a tradeoff between increasing additive distortion or receiver noise and increasing phase-drift variance; CLOs do not permit increasing phase-drift variance.Phase-drift variance can scale only logarithmically with N and is more constrained as coherence-block length T increases; smaller T and pilots distributed over the block allow larger variance.Source: C. Asymptotic Analysis and Hardware… · p. 7

IV. UTILIZING THE SCALING LAW: CIRCUIT-AWARE DESIGN

The paper applies its hardware scaling law to circuit-aware design, relating progressively lower per-circuit cost and power to sublinear growth as antenna count increases. Its discussion focuses on single-carrier flat-fading channels and notes that interpretation may differ for multi-carrier modulation.

IV. UTILIZING THE SCALING LAW: CIRCUIT-AWARE DESIGN

  • The mapping from a receiving-array circuit's imperfections to the model's distortion categories depends on the modulation scheme.For OFDM, phase-noise multiplicative distortion also produces additive noise-like inter-carrier interference.Source: §IV · p. 8
  • Circuit-aware design uses the scaling law to lower cost and power dissipation per circuit gradually, aiming for sublinear total cost and power growth with antenna count.The discussion concentrates on single-carrier transmission over flat-fading channels and briefly considers possible changes under multi-carrier modulation.Source: §IV · p. 8
  • The circuit implications are framed around the receiver components shown in Fig. 1, connecting hardware imperfections to circuit cost and power tradeoffs.The abstracted system model covers single-carrier flat-fading transmission, multicarrier subcarriers such as OFDM or FBMC, and to some extent frequency-selective single-carrier channels.Source: §IV · p. 8

A. Analog-to-Digital Converter (ADC)

The circuit examples translate the scaling law into antenna-branch design choices: ADC resolution and LNA noise amplification can be relaxed with N, while LO options have distinct scaling limits. These tradeoffs connect tolerated imperfections to circuit power and cost.

A. Analog-to-Digital Converter (ADC)

  • Reducing ADC resolution by around z1/2 log2(N) bits can lower per-antenna cost and complexity; with 256 antennas, the example permits 2 fewer bits per ADC.For separate ADCs per antenna, total ADC power scales as N^(1−z1) rather than N when z1 ≤ 1/2.Source: A. Analog-to-Digital Converter (ADC) · p. 8

B. Low Noise Amplifier (LNA)

  • For LNAs, allowing noise amplification to increase as N^z2 can reduce total power growth to N^(1−z2), rather than N.At z2 = 1/2, the noise figure can increase by 10 dB when deploying 100 antennas instead of one.Source: B. Low Noise Amplifier (LNA) · p. 8

C. Local Oscillator (LO)

  • With SLOs, total LO power NPLO increases almost linearly with N despite logarithmic reduction in per-LO power; in contrast, phase-noise variance cannot be scaled with a CLO.Regardless of LO type, inter-carrier interference is suppressed by z2·10 log10(N) dB. SLOs also allow carrier frequency fc to increase with N.Source: C. Local Oscillator (LO) · pp. 8–9

D. Non-Linearities

The numerical illustrations compare deployments and hardware settings, while the nonlinearity model represents nonlinear components as a scaled useful signal plus uncorrelated distortion. The simulations show that distributed arrays can substantially outperform co-located arrays, and that large-N rate loss depends strongly on oscillator and pilot choices.

D. Non-Linearities

  • For Gaussian transmit signals, the Bussgang model represents a nonlinear component as a scaled useful signal plus distortion uncorrelated with that signal.Depending on the nonlinearity, the distortion is included in distortion noise or receiver noise.Source: D. Non-Linearities · p. 9

V. NUMERICAL ILLUSTRATIONS

A. Comparison of Deployment Scenarios

  • Distributed deployment achieves roughly twice the rates of co-located massive MIMO, while SLO hardware keeps rate losses small and CLO hardware can lose 25% at N = 400.The paper attributes the distributed-array advantage to proximity gains together with array gains and spatial resolution from coherent processing.Source: A. Comparison of Deployment Scenarios · pp. 9–10, Figure 4 · p. 10

B. Validation of Asymptotic Behavior

  • As N grows, SLO rate loss is almost negligible, whereas CLO loss approaches 50%; temporal pilots' slight asymptotic rate gain appears only at impractically large N.Temporal pilots are preferred in this simulation because they use K times less pilot energy; at lower average SNR, spatial pilots can improve estimation accuracy.Source: B. Validation of Asymptotic Behavior · p. 10, Figure 5 · p. 10

C. Impact of Coherence Block Length

The section relates coherence-block and pilot choices to rate, then examines hardware-scaling behavior under MRC and MMSE and summarizes the paper’s asymptotic conclusions. It also identifies downlink analysis as future work.

C. Impact of Coherence Block Length

  • With hardware imperfections, average UE rates rise with coherence-block length T at small T but then fall as phase-drifts accumulate; with ideal hardware, rates rise slightly with T.For ideal hardware, pilot distribution has no impact; the pre-log penalty decreases as T grows with B fixed.Source: C. Impact of Coherence Block Length · p. 11
  • Middle-of-block pilots yield slightly higher rates and allow larger coherence blocks, while beginning-of-block pilots avoid buffering incoming signals while receive filters are computed.The pilot-position comparison concerns phase-drift accumulation and implementation convenience.Source: C. Impact of Coherence Block Length · p. 11

D. Hardware Scaling Laws with Different Receive Filters

  • Hardware imperfections satisfying the scaling law cause small MRC rate losses, while configurations that violate it faster lead to rates tending asymptotically to zero.The plotted comparison uses ideal hardware, fixed imperfections, and imperfections increasing with N.Source: D. Hardware Scaling Laws with… · p. 11, Figure 7 · p. 11
  • MMSE achieves higher rates than MRC, but its hardware-imperfection losses are larger because spatial interference suppression is sensitive to imperfections.The rate comparison uses different plot scales.Source: D. Hardware Scaling Laws with… · pp. 11–12, Figure 8 · p. 11

VI. CONCLUSION

  • As N grows, only phase-drifts limit achievable rates; uncorrelated distortions add non-coherently during receive processing.The paper attributes the non-coherent addition to distortions being uncorrelated with useful signals.Source: §VI · p. 12
  • Independent antenna phase-drift variance can grow logarithmically with N, but common-LO phase-drift variance cannot grow; the scaling law also supplies sufficient conditions for judicious filters beyond MRC.The transmission protocol must adapt to the rate at which phase-drifts deteriorate performance.Source: §VI · p. 12
  • The authors leave downlink analysis with BS hardware imperfections as a natural extension; the corresponding analytic details are outside this paper’s scope.They suggest that MRT may yield similar closed-form rate expressions and scaling laws, but do not derive them here.Source: §VI · p. 12

APPENDIX A: A USEFUL LEMMA

The appendices outline a Gaussian quadratic-form lemma, connect uncorrelated noise terms to LMMSE estimation, and explain how the achievable-rate bound treats interference and channel variation.

APPENDIX A: A USEFUL LEMMA

  • For u distributed as CN(0, Λ) and deterministic M, the lemma’s proof rewrites u^H M u using a whitened Gaussian vector and Λ^1/2 M Λ^1/2.The proof describes the result as following by straightforward computation.Source: Appendix A · p. 12

APPENDIX B: PROOF OF THEOREM 1

  • The LMMSE estimator follows from the general estimator expression, using that additive distortion and receiver noises are uncorrelated with the channel and user channels are independent.The appendix then obtains the estimator and its error covariance from the preceding expressions.Source: Appendix B · p. 12

APPENDIX C: PROOF OF LEMMA 1

  • The achievable-rate SINR treats uncorrelated inter-user interference and distortion as independent Gaussian noise, while channel deviations from the average effective channel are also treated as worst-case Gaussian noise.The derivation exploits only the average effective channel in detection.Source: Appendix C · p. 13

APPENDIX D: PROOF OF THEOREM 2

The proof derives Theorem 2’s expressions through expectations over channel, phase-drift, and distortion terms, using distinct phase-drift cases for common and separate oscillators.

APPENDIX D: PROOF OF THEOREM 2

  • The proof derives the theorem’s expressions term by term, beginning with moments involving the LMMSE estimate and its relation to the observation.It uses the estimate’s LMMSE properties to establish the first moment before expanding second-order moments.Source: Appendix D · p. 13
  • The phase-drift expectation depends on whether the system uses a common LO or separate LOs; the proof evaluates the corresponding cases separately.The expressions distinguish antenna indices for separate LOs and use the common-LO case separately.Source: Appendix D · pp. 13–14
  • The distortion-noise expectation separates independent covariance terms from statistically dependent terms before substituting the resulting expansions into the theorem expressions.The derivation also expands diagonal matrices and uses the Gaussian quadratic-form lemma.Source: Appendix D · p. 14

APPENDIX E: PROOF OF COROLLARY 3

The corollary proof rescales the SINR terms and inspects their asymptotic behavior using expressions established in Theorem 2.

APPENDIX E: PROOF OF COROLLARY 3

  • The proof divides the SINR terms by N^2 A^2 before inspecting their scaling as N tends to infinity.Source: Appendix E · p. 15
  • The asymptotic inspection uses expressions from Theorem 2 and the stated behavior of Ψ_A^-1.Source: Appendix E · p. 15
  • The proof identifies the terms that remain in the SINR as N tends to infinity.The supplied passage identifies these as A^2 terms.Source: Appendix E · p. 15

APPENDIX F: PROOF OF COROLLARY 4

The proof substitutes the new parameters into the SINR and compares the scaled asymptotic orders of its terms. It derives different nonvanishing conditions for SLO and CLO interference.

APPENDIX F: PROOF OF COROLLARY 4

  • After scaling, the distortion-noise and receiver-noise terms go to zero, while the signal numerator has order O(N^(1−2 max(z1,z2)−z3δ0 minτ|t−τ|)).Source: Appendix F · p. 15
  • For SLOs, the stated nonvanishing condition is 1 − 2 max(z1,z2) − z3δ0 minτ|t−τ| > 1.The second-order interference moments scale like the signal term.Source: Appendix F · p. 15
  • For CLOs, interference scales as O(N^(1−2 max(z1,z2))) independently of z3, requiring z3 = 0 and max(z1,z2) ≤ 1.Source: Appendix F · p. 15
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