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Cryogenic Control Architecture for Large-Scale Quantum Computing
J. M. Hornibrook, J. I. Colless, I. D. Conway Lamb, S. J. Pauka, H. Lu, A. C. Gossard, J. D. Watson, G. C. Gardner, S. Fallahi, M. J. Manfra, D. J. Reilly
TL;DR
The paper addresses the need for scalable classical control hardware for large solid-state quantum processors. It proposes a cryogenic architecture separating analog waveforms from digital addressing and demonstrates switching, modulation, and semiconductor-qubit control. The demonstration supports autonomous cryogenic control without detected additional noise or increased electron temperature, while power dissipation remains a scaling boundary.
Problem
Large-scale quantum processors require classical control hardware that is fast, low-noise, and scalable beyond brute-force room-temperature systems.
Method
The paper develops a distributed cryogenic PL/AL architecture that separates reusable analog prime waveforms from digital qubit addressing and routes them with switching matrices.
Results
No additional noise or increase in electron temperature was detected when a cryogenic FPGA and switching matrix configured a semiconductor quantum dot.
Takeaways & Limitations
The demonstrated architecture provides a path toward scaling classical support hardware for large-scale quantum computers and may improve few-qubit quantum-dot experiments.
Takeaways & Limitations
Power dissipation in cryogenic control systems may require improvements in refrigeration technology for large-scale quantum information processing.
Abstract
from arXiv · showhide
Solid-state qubits have recently advanced to the level that enables them, in-principle, to be scaled-up into fault-tolerant quantum computers. As these physical qubits continue to advance, meeting the challenge of realising a quantum machine will also require the engineering of new classical hardware and control architectures with complexity far beyond the systems used in today's few-qubit experiments. Here, we report a micro-architecture for controlling and reading out qubits during the execution of a quantum algorithm such as an error correcting code. We demonstrate the basic principles of this architecture in a configuration that distributes components of the control system across different temperature stages of a dilution refrigerator, as determined by the available cooling power. The combined setup includes a cryogenic field-programmable gate array (FPGA) controlling a switching matrix at 20 millikelvin which, in turn, manipulates a semiconductor qubit.
I. CONTROL MICRO-ARCHITECTURE
The PL/AL architecture separates reusable analog prime waveforms from digital addressing information, allowing a switching matrix to route universal gate operations and readout to selected qubits.
- I. CONTROL MICRO-ARCHITECTURE: Quantum algorithms can be implemented from repeated single- and two-qubit unitaries drawn from a small universal gate set.
- I. CONTROL MICRO-ARCHITECTURE: Analog prime waveforms are separated from digital addressing information that selects which qubit receives each waveform during the algorithm.The same microwave waveforms can be reused rather than generated and transmitted separately for every qubit.
- I. CONTROL MICRO-ARCHITECTURE: Prime-lines carrying a universal gate set are routed to selected qubits through a switching matrix controlled by address-lines.
- I. CONTROL MICRO-ARCHITECTURE: The architecture executes the algorithm through timed address-line selections that direct appropriate prime waveforms to qubits or qubit pairs.Readout uses the address bus similarly to select a qubit or readout device.
II. IMPLEMENTATION OF THE CONTROL ARCHITECTURE
The control architecture distributes hardware across cryostat temperature stages, placing switching near qubits while using cryogenic logic and multiplexing to limit wiring, heat, latency, and noise constraints.
- II. IMPLEMENTATION OF THE CONTROL ARCHITECTURE: Subsystems are distributed across cryostat stages because cooling power differs substantially between the 4 K and 20 mK stages.The 4 K stage typically provides ∼1 W, whereas the 20 mK stage provides less than 1 mW.
- II. IMPLEMENTATION OF THE CONTROL ARCHITECTURE: Cryogenic logic at 4 K supplies addressing information to a millikelvin switching matrix that steers control pulses near the qubits.The 4 K logic also interfaces with multiplexed readout and digital-to-analog converters.
- II. IMPLEMENTATION OF THE CONTROL ARCHITECTURE: Locating the switching matrix close to the qubits reduces latency and synchronization challenges associated with propagation over centimetre-scale wavelength distances.
- II. IMPLEMENTATION OF THE CONTROL ARCHITECTURE: Multiplexed data on a small number of transmission lines can be decoded to operate many parallel switches, reducing wiring and interconnect density.This multiplexing is expected to be important because numerous parallel lines add cryogenic heat load.
- II. IMPLEMENTATION OF THE CONTROL ARCHITECTURE: Variable-impedance switching elements can adjust each waveform’s amplitude and phase and support calibration for device-to-device parameter variation.
A. HEMT Switching Elements
The prototype HEMT switch uses gate-controlled depletion of a two-dimensional electron gas to reflect or transmit microwave signals, achieving nanosecond-scale switching.
- A. HEMT Switching Elements: A negative top-gate voltage pinches off the 2DEG channel, increasing impedance and reflecting the input signal.In the on-state, the coplanar waveguide is configured near ∼50 Ω characteristic impedance.
- A. HEMT Switching Elements: A 120 MHz sine wave propagates to the output when the gate voltage is zero and is blocked otherwise.
- A. HEMT Switching Elements: 1–2 ns switching time is indicated by sidebands generated when a 5 GHz carrier is modulated through the 2DEG.The measured prototype switching time is of order 1 ns.
- A. HEMT Switching Elements: Ion implantation can improve contact resistance and capacitance while substantially shrinking the device footprint.
B. Capacitive Switching Elements
The capacitive switch controls transmission by depleting a 2DEG ground plane, providing broadband isolation and a higher-frequency alternative to the HEMT design with a footprint trade-off.
- B. Capacitive Switching Elements: A negative gate bias depletes the 2DEG ground plane, reducing capacitance, changing impedance, and reflecting the input signal.
- B. Capacitive Switching Elements: The capacitive switch performs better at higher frequency than the HEMT switch but occupies a larger footprint because of impedance tapering and the coplanar-to-microstrip transition.
- B. Capacitive Switching Elements: An all-microstrip design near 200 Ω significantly reduces the required footprint.
C. 2:2 Switch Matrix
The 2:2 cryogenic routing matrix switches signals between two inputs and two outputs, while gate voltages control transmission paths and output amplitude. IQ modulation further enables adjustable phase and amplitude for qubit-specific calibration.
- 2:2 routing matrix: Two input ports are split across two output ports, with gate voltages V_i,j controlling the transmission parameters S_ij.The output ports include bias tees for semiconductor quantum-dot qubits.
- 2:2 routing matrix: The matrix switches between paths with negligible crosstalk, showing less than 0.05 dB response change when the other path is switched.
- IQ modulation: IQ modulation combines sine and cosine inputs to produce tones with calibrated phase and amplitude controlled by gate voltages.The integrated matrix can compensate for parameter variation between physical qubits by adjusting each qubit's connection to the prime waveform bus.
IV. CRYOGENIC LOGIC
The architecture places fast classical logic between a compiled quantum algorithm and the cryogenic switching matrix. Technology selection depends on qubit coherence, control bandwidth, and the number of simultaneously controlled qubits.
- Cryogenic logic: A fast classical-logic layer interfaces the compiled quantum algorithm with the switching matrix through an address bus.It also supports feedback for qubit stabilisation, readout conditioning, and open-loop error suppression.
- Cryogenic logic: Control technology is selected according to qubit coherence times, control-signal bandwidth, and the number of simultaneous qubits.
- Cryogenic logic: With solid-state qubit coherence approaching 1 millisecond, CMOS FPGAs or ASICs operating at 4 kelvin are viable control platforms.Longer-term higher-performance options include InP, SiGe BiCMOS, and superconducting flux logic.
- Cryogenic logic: The demonstration uses a commercial Xilinx Spartan-3A FPGA made operational at the 4 K stage of a dilution refrigerator.A custom cryogenic printed circuit board supports operation with components whose parameters vary little at cryogenic temperatures.
V. SEMICONDUCTOR QUBIT CONTROL
The experiment combines a room-temperature waveform generator, a cryogenic FPGA, and a millikelvin switching matrix to control a GaAs double quantum dot. FPGA-directed waveforms reproduce charge-stability features without detectable added noise or heating.
- Semiconductor qubit control: A GaAs double quantum dot in the few-electron regime is controlled autonomously by combining the cryogenic control building blocks.The architecture aims to avoid additional noise or heating to the quantum system.
- Semiconductor qubit control: A single room-temperature coaxial cable feeds a 100 kHz square-wave prime waveform into the 2:2 matrix, whose outputs connect to plunger gates LP and RP.The 4 kelvin FPGA steers the waveform by opening and closing matrix switches in response to commands from room temperature.
- Semiconductor qubit control: With matrix switches off, rf-QPC sensing produces a standard charge-stability diagram, indicating sufficiently high isolation between input and output ports.
- Semiconductor qubit control: Directing the square wave to either or both plunger gates produces two copies of the charge-stability diagram.The copies arise because the 50% duty-cycle waveform configures two distinct charge states offset by ΔV_R or ΔV_L.
- Semiconductor qubit control: No additional noise or increase in electron temperature, approximately 100 mK, is detected relative to the bare quantum dot.
VI. DISCUSSION
The demonstrated multi-component architecture suggests a route toward scaling classical support for large quantum computers and offers near-term uses in few-qubit experiments. Scaling remains constrained by the power dissipated by cryogenic control systems.
- Discussion: The architecture provides a path for scaling the classical support system required to operate a large-scale quantum computer.
- Discussion: Multiple out-of-phase waveform copies could suppress crosstalk by cancelling voltage capacitively coupled to neighbouring surface gates.
- Discussion: A high-frequency cryogenic multiplexer could automate testing and characterisation of many devices during one cool-down experiment.
- Discussion: Large-scale quantum information processing will likely require improved cryogenic refrigeration because of the power dissipation inherent in the control systems.
VII. CONCLUSION
The paper proposes a cryogenic control micro-architecture that separates analog waveforms from digital qubit addressing. It demonstrates feasibility by controlling a semiconductor qubit with a cryogenic FPGA and custom low-temperature switching matrix.
- The proposed micro-architecture separates analog control prime waveforms from digital addressing to support scaling to computation-sized qubit counts.
- A semiconductor qubit was controlled using a cryogenic FPGA system and custom switching matrix for steering analog waveforms at low temperature.
- Integrated, autonomous control systems are anticipated to become increasingly important for developing and demonstrating fault-tolerant quantum machines.
VIII. METHODS AND MATERIALS
The GaAs switching elements use a fabrication procedure similar to that of quantum-dot devices, supporting easy integration.
- GaAs switching elements follow a fabrication procedure similar to quantum-dot devices, allowing easy integration.
- The mesa is wet etched using sulphuric acid before Au/Ge/Ni ohmic contacts are thermally evaporated and annealed at 470 degrees for 100 seconds.
- The final metal layer is thermally evaporated TiAu with thicknesses of 10 nm / 100 nm.
X. AUTHOR CONTRIBUTIONS
The listed contributors divided responsibilities across architecture design, device fabrication, heterostructure growth, experiments, and manuscript preparation.
- D.J.R. devised the micro-architecture, while J.M.H. fabricated the switches and switching matrix.
- Several contributors grew heterostructures for the switches and quantum dot, including M.J.M., J.D.W., G.G., S.F., H.L., and A.C.G.
- Experiments covered the switches and the quantum dot with FPGA control, and J.M.H. and D.J.R. wrote the manuscript.