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A Complementary Resistive Switch-based Crossbar Array Adder

A. Siemon, S. Menzel, R. Waser, E. Linn

arXiv:1410.2031v2cs.ET

TL;DR

Passive nanocrossbars offer compact ReRAM storage, but sneak currents constrain arrays without selectors or CRS cells, and CRS logic had previously been demonstrated only for basic operations. This paper presents two multi-bit CRS adder schemes and evaluates them with SPICE simulations, reporting a trade-off between fewer steps and fewer devices.

  • Problem

    Passive crossbar arrays are compact, but low-resistance devices cause sneak currents that limit array size without selectors or CRS configurations, while CRS logic had only been shown for basic Boolean functions.

    Source: §I · p. 1

  • Method

    The paper develops two bit-serial adder schemes for passive CRS crossbars and verifies their operation using SPICE simulations with a dynamical memristive device model.

    Source: §III · p. 3, A. ReRAM Device Modeling · p. 7

  • Results

    The Precalculation-Adder requires the fewest steps, while the Toggle-Cell-Adder uses about half the devices but requires 4N+5 cycles, compared with 2(N+1)+2 for the Precalculation-Adder.

    Source: §8 · p. 5, §13 · p. 6, §VI · p. 10

  • Takeaways & Limitations

    The two schemes enable multi-bit logic operations in CRS arrays, with the Precalculation-Adder minimizing steps and the Toggle-Cell-Adder minimizing cell count.

    Source: §VI · p. 10

Abstract

from arXiv · show

Redox-based resistive switching devices (ReRAM) are an emerging class of non-volatile storage elements suited for nanoscale memory applications. In terms of logic operations, ReRAM devices were suggested to be used as programmable interconnects, large-scale look-up tables or for sequential logic operations. However, without additional selector devices these approaches are not suited for use in large scale nanocrossbar memory arrays, which is the preferred architecture for ReRAM devices due to the minimum area consumption. To overcome this issue for the sequential logic approach, we recently introduced a novel concept, which is suited for passive crossbar arrays using complementary resistive switches (CRSs). CRS cells offer two high resistive storage states, and thus, parasitic sneak currents are efficiently avoided. However, until now the CRS-based logic-in-memory approach was only shown to be able to perform basic Boolean logic operations using a single CRS cell. In this paper, we introduce two multi-bit adder schemes using the CRS-based logic-in-memory approach. We proof the concepts by means of SPICE simulations using a dynamical memristive device model of a ReRAM cell. Finally, we show the advantages of our novel adder concept in terms of step count and number of devices in comparison to a recently published adder approach, which applies the conventional ReRAM-based sequential logic concept introduced by Borghetti et al.

I. INTRODUCTION

ReRAM suits dense memory and logic, but passive crossbars need a selector or complementary resistive switches (CRSs) to limit sneak currents. This paper extends CRS-based stateful logic to multi-bit addition and describes the crossbar system that supports consecutive operations.

I. INTRODUCTION

  • ReRAM stores information in low- and high-resistance states, and both VCM and ECM cells support bipolar SET and RESET switching.The introduction describes VCM switching through oxygen-vacancy movement and ECM switching through metallic Cu or Ag filaments.Source: §I · p. 1
  • Passive arrays can reach 4F2 device area, but low-resistance cells create sneak paths that limit array size without selectors or CRS configurations.The paper proposes extending hybrid CMOS/crossbar architectures from memory operations to logic-in-memory operations.Source: §I · p. 1, A. Passive crossbar arrays · p. 2
  • The paper shows that adder concepts for its logic approach are feasible and superior to previous approaches in cycle and element count, whereas earlier Borghetti logic demonstrations showed only basic functions such as IMP or NAND.Lehtonen et al. suggested an adder using Borghetti’s approach; Kvatinsky et al. represented two improved concepts.Source: §I · p. 1

A. Passive crossbar arrays

  • The proposed hybrid system uses a CMOS control unit to address wordlines and bitlines across arrays, with control-unit communication enabling consecutive logic operations.The illustrated example has two arrays, each with three wordlines and five bitlines.Source: A. Passive crossbar arrays · p. 2, Figure 1 · p. 2

B. Complementary Resistive Switches

CRS cells use two anti-serial ReRAM devices to store both logical values in high-resistance states. Their stateful switching supports many Boolean functions, including one-step carry calculation, while a sum requires two steps and access to the next carry.

B. Complementary Resistive Switches

  • A CRS stores 0 as LRS/HRS and 1 as HRS/LRS; its ON state is transitional during switching, while half-select operation uses low, high, and ground levels and requires steep switching kinetics.Source: B. Complementary Resistive Switches · p. 2

C. CRS single-bit logic operations

  • The prior CRS state selects reverse implication when it is 1 and inverse implication when it is 0, making 14 of 16 Boolean functions directly feasible; XOR and XNOR require a second CRS cell.The state-transition relation is presented as a basis for CRS-logic synthesis.Source: C. CRS single-bit logic operations · p. 2

D. CRS carry bit and sum bit calculation

  • Carry calculation is intrinsic to CRS logic and takes one step, whereas sum calculation takes two steps using an intermediate state and the next carry as an input.Because read-out is destructive, the next carry must be computed in another cell or written back; carry and the first sum step can share a cycle in separate devices.Source: D. CRS carry bit and sum bit calculation · p. 3

III. ADDER SCHEMES

The paper presents two bit-serial addition schemes for passive CRS crossbars, where stored information can serve as an input to later operations. The schemes use parallel array operations to address the difficulty of moving information between stages in passive devices.

III. ADDER SCHEMES

  • The adder schemes perform multi-bit addition through consecutive signal sequences, using parallel array operations to ease the multiple steps required by sequential logic.The schemes build on single-bit carry and sum operations.Source: §III · p. 3
  • Passive CRS cells cannot pass information to the next stage, so multi-step calculations need intermediate information to be read out or retained for later use.Destructive read-out may require writing information back; using stored information as a later input is presented as preferable and potentially faster and more energy efficient.Source: §III · pp. 3–4
  • The paper explains the schemes using two-bit two’s-complement addition, for which three devices store the resulting word.The XOR needed for sum calculation is implemented in two steps using information from an auxiliary calculation as an input.Source: §III · p. 4

A. Precalculation-Adder

The Precalculation-Adder uses separate calculation and auxiliary wordlines in two arrays. It initializes and prepares intermediate information before merging it to complete the sum.

A. Precalculation-Adder

  • The Precalculation-Adder uses two wordlines in two arrays: one computes the sum and the other performs auxiliary calculations that are read out to complete it.Its operations are grouped into initialization, preparation, and finishing blocks; the latter two depend on operand length.Source: A. Precalculation-Adder · p. 4

1. Step: Initialize/read-out

  • The first step reads out stored information and brings the cells to a known state of 1.Source: §1 · p. 4

2. Step: Programming c0 in the calculation cells

  • The second step programs the first carry c0 into all calculation cells by setting wordlines to c0 and bitlines to 1, enabling distributed calculation and two’s-complement subtraction.Source: §2 · p. 4
  • In subsequent calculations, the least-significant calculation cell produces an intermediate sum state while other cells compute carries; auxiliary cells compute carries needed for final sums.Higher-significance cells then prepare further intermediate sum states and carries, including an additional MSB calculation to secure the result with doubled MSBs.Source: §3 · p. 4, §4 · p. 4, §5 · p. 5

6. Step: Read-out auxiliary result c1 and calculation of s0

The sixth step reads the LSB of wl_aux and uses it with b0 at wl_calc to calculate s0; the seventh and eighth steps similarly calculate s1 and s2.

6. Step: Read-out auxiliary result c1 and calculation of s0

  • The sixth step reads the LSB of wl_aux and applies it with b0 at wl_calc to calculate s0.Source: §6 · p. 5

7. Step: Read-out auxiliary result c2 and calculation of s1

  • The seventh and eighth steps similarly calculate s1 and s2.Source: §7 · p. 5

8. Step: Read-out auxiliary result c3 and calculation of s2

The Precalculation-Adder stores its sum in wl_calc after eight steps, with step count given as 2(N+1)+2. The Toggle-Cell-Adder uses fewer cells but more steps, with a toggle cell computing carries.

8. Step: Read-out auxiliary result c3 and calculation of s2

  • After eight steps, the sum is stored in wl_calc, and the stated step count is 2(N+1)+2 for operand bit length N.Source: §8 · p. 5, Figure 3 · p. 5

B. Toggle-Cell-Adder

  • The Toggle-Cell-Adder uses one wordline in one array and fewer cells, but requires more steps; its toggle cell computes all carry bits.Source: B. Toggle-Cell-Adder · p. 5

1. Step: Initialize/read-out

  • The first step reads out the last information and initializes the cells to a known state.Source: §1 · p. 5

2. Step: Programming c0 in the calculation cells

  • The second step programs c0 into all calculation cells by setting wl to c0 and the bitlines to ‘1’, enabling distributed calculation and two’s complement subtraction.Source: §2 · p. 5

4. Step: c1 is read out

The fourth step reads out the auxiliary carry c1; the following steps calculate s0 in the LSB and write c1 back to the toggle cell.

4. Step: c1 is read out

  • In the fourth step, only the toggle cell is read out.Source: §4 · p. 6

5. Step: Calculation of s0

  • The fifth step calculates s0 in the LSB by applying b0 at the wordline and the read-out c1 at bl1.Source: §5 · p. 6

6. Step: Writing back c1

  • The sixth step writes c1 back to the toggle cell, completing the LSB computation while its information remains stored until read out.Source: §6 · p. 6

8. Step: c2 is read out

The toggle cell is read out between sum-bit calculations, while the cells compute carries and intermediate states and write carries back for later steps.

8. Step: c2 is read out

  • In the eighth step, the toggle cell is read out again.Source: §8 · p. 6

9. Step: Calculation of s1

  • Step nine calculates s1 in A0CRSwl0bl2 using b1 at the wordline and the read-out c2 at bl2.Source: §9 · p. 6

10. Step: Writing back c2

  • In the tenth step, the toggle cell is written back.Source: §10 · p. 6
  • The eleventh step prepares the MSB by calculating an intermediate state and computes the last carry c3 in the toggle cell.Source: §11 · p. 6

12. Step: c3 is read out

  • In step twelve, the toggle cell is read out for the last time in this example.Source: §12 · p. 6

13. Step: Calculation of s2

The Toggle-Cell-Adder uses more cycles than the Precalculation-Adder but requires about half as many devices. The ECM simulations characterize switching polarity and show why the CRS ON-window width does not affect the applied read/write scheme.

13. Step: Calculation of s2

  • The Toggle-Cell-Adder uses 4N+5 cycles versus 2(N+1)+2 for the Precalculation-Adder, while requiring about half as many devices.The cycle-flow graph is shown in Fig. 4.Source: §13 · p. 6, Figure 4 · p. 7

A. ReRAM Device Modeling

  • The ECM model represents an Ag filament growing from Pt toward an Ag electrode, with electronic current controlled by the tunneling gap x.The authors use the model for higher-accuracy simulations and implement its equations in VerilogA, solved using Spectre.Source: A. ReRAM Device Modeling · p. 7
  • The ECM device's asymmetric SET (~1.3 V) and RESET (~-0.5 V) voltages narrow the CRS ON-window, but its width does not affect performance with the applied Spike read scheme.The read fully switches LRS/HRS to HRS/LRS; a Level read using the LRS/LRS state is also described as feasible due to nonlinear device kinetics.Source: A. ReRAM Device Modeling · p. 8, Figure 6 · p. 8
  • The VerilogA crossbar simulations use the dynamic ECM model to demonstrate the adder schemes, with control signals adjusted manually.The model's gap decreases for positive cell voltage (SET) and increases for negative current (RESET).Source: Figure 5 · p. 7, A. ReRAM Device Modeling · p. 8

B. Simulation of the Precalculation-Adder

The Precalculation-Adder simulation separates carry and intermediate-sum preparation from final sum-bit computation. The Toggle-Cell-Adder simulation instead reads and writes back a toggle cell between bit calculations; both figures illustrate an example with inputs a = 01 and b = 01.

C. Simulation of the Toggle- Cell-Adder

B. Simulation of the Precalculation-Adder

  • The Precalculation-Adder computes carry and intermediate-sum information in steps 3–5, then merges it to calculate final sum bits in steps 6–8.The simulated example uses a = 01 and b = 01, followed by a readout to verify the stored result.Source: B. Simulation of the… · p. 8, Figure 7 · p. 9

C. Simulation of the Toggle- Cell-Adder

  • The Toggle-Cell-Adder calculates carry and intermediate-sum information in steps 3, 7, and 11, reading the toggle cell and writing information back between sum-bit calculations.For the a = 01, b = 01 example, the final sum bits are computed in steps 5, 9, and 13, followed by a result readout.Source: C. Simulation of the Toggle- Cell-Adder · p. 8, Figure 8 · p. 9

V. ADDER COMPARISON

The new adder schemes use fewer devices and cycles than the compared approaches, and operate on 4F2 passive crossbar arrays. The Toggle-Cell-Adder minimizes cell count, while the Precalculation-Adder minimizes steps.

V. ADDER COMPARISON

  • The newly introduced schemes require fewer devices and cycles, and these adders work on 4F2 passive crossbar arrays; in contrast, Kvatinsky’s parallel approach needs a more complex crossbar architecture.Source: §V · p. 10
  • The Precalculation-Adder needs global interconnect to transfer read-out information between arrays, while the TC-Adder can store that information in the same wordline.For the TC-Adder, the information is needed in two more cycles, so it must be sent to the control unit or stored in a register if near interconnect is available.Source: §V · p. 10

VI. CONCLUSION

  • The Toggle-Cell-Adder uses the fewest cells, whereas the Precalculation-Adder requires the fewest steps.Both schemes enable multi-bit logic operations in CRS arrays and could pave the way for computing architectures based on ReRAM-type nanocrossbar memories.Source: §VI · p. 10
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