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Deep Learning with Limited Numerical Precision
Suyog Gupta, Ankur Agrawal, Kailash Gopalakrishnan, Pritish Narayanan
TL;DR
Large-scale deep-network training is constrained by computational resources, while the need for high-precision computation during learning is uncertain. The paper studies low-precision fixed-point training with stochastic rounding and reports near-equivalent classification performance at 16 bits, alongside an energy-efficient accelerator. Its scope is bounded by degradation and stalled progress at still lower precision.
Problem
Training large-scale deep neural networks requires substantial computational resources, motivating investigation of whether limited-precision computation can support training.
Method
The paper combines low-precision fixed-point arithmetic and stochastic rounding with a hardware-software co-design approach for deep-network training and matrix multiplication.
Results
16-bit fixed-point training with stochastic rounding achieves nearly the same performance as 32-bit floating-point training on MNIST and CIFAR10, while the FPGA accelerator reaches 260 G-ops/s at 37 G-ops/s/W.
Takeaways & Limitations
Stochastic rounding makes low-precision fixed-point deep-network training viable while supporting high-throughput, low-power hardware.
Takeaways & Limitations
Reducing precision to 12 bits degrades convergence and causes SGD to stop making progress, with minimum test error saturating at 28.8%.
Abstract
from arXiv · showhide
Training of large-scale deep neural networks is often constrained by the available computational resources. We study the effect of limited precision data representation and computation on neural network training. Within the context of low-precision fixed-point computations, we observe the rounding scheme to play a crucial role in determining the network's behavior during training. Our results show that deep networks can be trained using only 16-bit wide fixed-point number representation when using stochastic rounding, and incur little to no degradation in the classification accuracy. We also demonstrate an energy-efficient hardware accelerator that implements low-precision fixed-point arithmetic with stochastic rounding.
1. Introduction
The paper motivates hardware-software co-design for deep-network training by exploiting neural networks’ error resilience and tolerance to noise. It investigates low-precision fixed-point arithmetic, emphasizing rounding mode, and reports near-floating-point performance with 16-bit stochastic rounding.
- Fast supervised training on large labeled datasets enables rapid architecture evaluation and hyperparameter search, motivating specialized deep-learning infrastructure.
- Neural networks tolerate statistical approximation errors, and added training noise can improve performance, reducing the need for high-precision computation.
- The proposed cross-layer strategy exposes approximate, possibly nondeterministic hardware computations to algorithms while preserving the programming model.
- Fixed-point units are motivated by their typically higher speed and lower hardware-resource and power requirements than floating-point engines.
- 16-bit fixed-point training with stochastic rounding achieves nearly the performance of 32-bit floating-point training on MNIST and CIFAR10.
2. Related Work
Prior work studied precision choices for neural-network hardware and limited-precision training, but largely focused on inference or shallow networks. This paper addresses deep-network training with 16-bit fixed-point arithmetic and stochastic rounding, contrasting with earlier 32-bit requirements.
- Most precision studies target feed-forward inference, assuming offline training with high-precision computations.
- Earlier limited-precision training studies often examined single-hidden-layer perceptrons with few hidden units, limiting direct extrapolation to modern deep networks.
- Earlier deep-network accelerator work required 32-bit fixed-point representation for convergence on MNIST, whereas this paper reports 16-bit training with stochastic rounding.
3. Limited Precision Arithmetic
The paper represents neural-network values with fixed-point formats defined by integer and fractional widths, then converts accumulated results through clipping or rounding. It emphasizes stochastic rounding as a distinct conversion choice and describes a two-step inner-product implementation that preserves accumulation precision before conversion.
- Fixed-point representation: Fixed-point word length is WL = IL + FL, with FL determining precision and ε = 2^-FL setting the smallest representable positive increment.The notation ⟨IL, FL⟩ identifies integer and fractional widths; higher FL means higher precision under the paper’s definition.
- Rounding modes: Rounding converts a higher-precision value x to the target ⟨IL, FL⟩ grid, where ⌊x⌋ is the largest multiple of ε not exceeding x.The paper treats the rounding mode used during this conversion as important for fixed-point computation.
- Rounding modes: Stochastic rounding selects the lower or upper neighboring representable value with probabilities proportional to x’s proximity to each one.Its expected rounding error is zero, making it an unbiased rounding scheme.
- Conversion behavior: Values outside the target fixed-point range are saturated to the format’s lower or upper limit regardless of rounding mode.This conversion behavior is specified separately from the choice between deterministic and stochastic rounding.
- Multiply and accumulate (MACC) operation: The inner product first accumulates products in a wider temporary register, then converts the result to the target format by clipping or rounding.Each product uses ⟨2 × IL, 2 × FL⟩, while the worst-case accumulator width is log2d + 2WL.
- Multiply and accumulate (MACC) operation: Delaying rounding until after accumulation reduces stochastic-rounding hardware overhead and matches FPGA DSP accumulation behavior.The same two-step approach also supports efficient CPU/GPU simulation of fixed-point computations.
4. Training Deep Networks
The experiments evaluate 16-bit fixed-point training across MNIST and CIFAR10 networks, showing that stochastic rounding generally preserves learning better than round-to-nearest. Precision limits still constrain convergence, but selective higher-precision fine-tuning can recover performance.
- Training Deep Networks: 16-bit fixed-point representations divide bits between integer and fractional parts, creating risks of lost updates and clipped activation outputs.The format uses a fixed word length, so increasing fractional precision reduces integer range.
- Training Deep Networks: Stochastic rounding preserves MNIST DNN learning at lower precision, whereas round-to-nearest increasingly harms learning as fractional precision falls below 14 bits.The paper attributes this difference to stochastic rounding preserving small updates statistically rather than always mapping them to zero.
- Training Deep Networks: 0.83% and 0.90% test error were achieved on the MNIST CNN with stochastic rounding at 14-bit and 12-bit precision, versus a 0.77% float baseline.Round-to-nearest failed to converge for this CNN, and layer outputs used the ⟨6, 10⟩ format.
- Training Deep Networks: 25.4% test error was achieved on CIFAR10 with 14 fractional bits and stochastic rounding, close to the 24.6% floating-point baseline.Round-to-nearest training began to collapse after a few epochs under the described 16-bit configuration.
- Training Deep Networks: 28.8% minimum test error resulted at 12-bit precision before increasing word length from 16 to 20 bits restored performance toward the float result.After 100 epochs at ⟨4, 12⟩, 15–20 further epochs at ⟨4, 16⟩ produced rapid improvement.
- Training Deep Networks: Mixed-precision training first uses low-precision fixed-point arithmetic with stochastic rounding, then applies a few higher-precision epochs when learning stagnates.The paper presents this as a potentially more robust training strategy.
5. Hardware Prototyping
The paper prototypes an FPGA accelerator for fixed-point matrix multiplication, targeting faster and more power-efficient training while accounting for FPGA development cost and memory-bandwidth constraints.
- Hardware Prototyping: GEMM operations dominate mini-batch stochastic-gradient-descent execution, so improving GEMM throughput can reduce training time.The relevant operations occur in feed-forward, back-propagation, and weight-update steps.
- Hardware Prototyping: FPGAs were selected for faster development and lower cost than ASICs, while their fixed-point DSP units suit the proposed arithmetic.The design must still manage limited memory bandwidth carefully.
- Hardware Prototyping: The prototype uses a Xilinx Kintex325T FPGA card with 840 DSP multiply-accumulate units, nearly 2 MB of block RAM, and 6.4 GB/s DDR3 bandwidth.Large matrices are stored in external DDR3 memory because they do not fit entirely on-chip.
5.1. System Description
The accelerator tiles matrix inputs into FPGA-resident blocks, reuses them across computations, and uses double buffering to hide memory-transfer latency.
- 5.1. System Description: The multiplier loads n columns of B and pn rows of A to compute pn² output elements, repeating until all matrix rows and columns are processed.The sequence partitions both matrices according to on-chip memory capacity.
- 5.1. System Description: Double buffering hides the latency of bringing new matrix subsets into the FPGA.This overlaps data movement with computation.
- 5.1. System Description: Input reuse lets each loaded element of A serve m times and each loaded element of B serve pn times, improving DDR3 bandwidth utilization.The reuse pattern is a direct consequence of the tiled operation sequence.
DSP FIFO MACC
The supplied passage is a hardware diagram label rather than a substantive description of the DSP FIFO MACC subsection.
- DSP FIFO MACC: The passage lists DSP, MACC, FIFO, and Input A as hardware labels without describing their roles or data flow.No additional operation or comparison is stated in the supplied text.
DSP DSP DSP FIFO FIFO
The systolic core streams matrix elements through local FIFO-connected DSP units, accumulating partial products and then applying stochastic rounding before output. Wavefront scheduling resets completed units early to sustain throughput.
- Systolic core: DSP MACC nodes multiply and accumulate streamed matrix elements, with row and column data staged in local FIFO queues.Each FIFO holds elements from a row of A or a column of B; values cascade right or downward through the array.
- Systolic core: Local neighbor-to-neighbor connections limit interconnect delays and improve the array’s maximum operating frequency.
- Wavefront operation: Wavefront scheduling transfers a completed result to a local register and resets its DSP after k cycles, before all other elements finish.This frees the unit to receive data from the next matrix multiplication while the pipeline continues.
- Output processing: Accumulated results are rounded by trimming least significant bits and truncating excess most significant bits after overflow or underflow detection.An LFSR supplies the random number used for stochastic rounding, while DSP pattern detection checks excess MSBs.
5.3. Results
The FPGA implementation combines high throughput with substantially higher power efficiency than the compared CPU and GPUs. The section also describes a compact stochastic-rounding implementation that removes a full multi-bit comparison.
- Hardware results: 260 G-ops/s at 37 G-ops/s/W were estimated for the 28x28 Kintex-K325T systolic array.The design used an estimated 166 MHz maximum frequency and 7 W power consumption.
- Hardware results: 37 G-ops/s/W compares favorably with the Intel i7-3720QM, NVIDIA GT650m, and GTX780, which achieve 1-5 G-ops/s/W.
- Rounding implementation: The presented stochastic-rounding approach removes the first full multi-bit comparison and enables compact implementation on a single DSP unit.It achieves the same result as direct multi-bit magnitude comparison followed by conditional addition and excess-MSB examination.
6. Conclusion
The paper argues for hardware-software co-design that exploits neural-network noise tolerance to reduce precision while preserving training performance. It combines fixed-point arithmetic, stochastic rounding, and an efficient matrix-multiplication architecture.
- Conclusion: The paper uses neural-network noise tolerance to influence the design of low-level compute units.
- Conclusion: Fixed-point arithmetic can improve energy efficiency and computational throughput while potentially risking neural-network performance.
- Conclusion: Stochastic rounding makes low-precision fixed-point training deliver results nearly identical to 32-bit floating-point computations.
- Conclusion: The architecture incorporates stochastic rounding into high-throughput, energy-efficient matrix multiplication with very little overhead.