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A CMOS Spiking Neuron for Brain-Inspired Neural Networks with Resistive Synapses and In-Situ Learning
Xinyu Wu, Vishal Saxena, Kehan Zhu, Sakkarapani Balagopal
TL;DR
Dense resistive-synapse systems need a compact neuron that can integrate spikes, drive many synapses, and support in-situ learning. This paper presents a dual-mode CMOS IFN using one opamp for integration and synaptic drive. Measurements report thousand-synapse drive, compact area and energy use, and in-situ associative learning.
Problem
Large-scale neuromorphic systems need a compact neuron that can support in-situ learning while driving many resistive synapses.
Source: §I · p. 1Method
A CMOS event-driven IFN reconfigures a single opamp for current integration and resistive-synapse drive, with programmable STDP-compatible spikes.
Source: §I · p. 1, A. Event-driven Dual-mode Operation · p. 3, B. STDP-Compatible Spike Generation · p. 4Results
More than one thousand synapses were driven with 0.01mm2 area and 9.3pJ/spike/synapse energy use, and a test chip demonstrated in-situ associative learning.
Source: §I · p. 1, §IV · pp. 4–5Takeaways & Limitations
Digital tunability provides flexibility to integrate with a broad range of resistive synapses and device material systems.
Source: §IV · p. 5The fabricated chip primarily verifies the neuron architecture with a range of devices, leaving scope to optimize layout size and power.
Source: §V · p. 5
Abstract
from arXiv · showhide
Nanoscale resistive memories are expected to fuel dense integration of electronic synapses for large-scale neuromorphic system. To realize such a brain-inspired computing chip, a compact CMOS spiking neuron that performs in-situ learning and computing while driving a large number of resistive synapses is desired. This work presents a novel leaky integrate-and-fire neuron design which implements the dual-mode operation of current integration and synaptic drive, with a single opamp and enables in-situ learning with crossbar resistive synapses. The proposed design was implemented in a 0.18 $\mu$m CMOS technology. Measurements show neuron's ability to drive a thousand resistive synapses, and demonstrate an in-situ associative learning. The neuron circuit occupies a small area of 0.01 mm$^2$ and has an energy-efficiency of 9.3 pJ$/$spike$/$synapse.
I. INTRODUCTION
The paper targets a compact CMOS neuron that can integrate spikes, drive dense resistive synapses, and support in-situ learning. Its dual-mode IFN is experimentally demonstrated with associative learning and reported area and energy figures.
I. INTRODUCTION
- Existing silicon neurons either fail to accommodate resistive synapses, require added learning circuitry, or incur significant overhead to drive large resistive loads.These constraints limit the high-density integration sought for large-scale systems.Source: §I · p. 1
- The proposed event-driven IFN uses dual-mode operation for spike integration and resistive-synapse driving, and generates digitally programmable STDP-compatible spikes.It connects directly to crossbar arrays of two-terminal resistive synapses for in-situ learning.Source: §I · p. 1
- The IFN was implemented in 0.18μm CMOS, drove more than one thousand synapses, occupied 0.01mm2, and consumed 9.3pJ/spike/synapse.A test chip with three neurons demonstrated in-situ associative learning.Source: §I · p. 1
- The neuron is presented as a building block for monolithic integration with nanoscale resistive synapses in large-scale brain-inspired architectures.Such architectures are expected to support energy-efficient, real-time machine learning systems.Source: §I · p. 1
II. BRAIN-INSPIRED NEUROMORPHIC SYSTEM
A neuromorphic unit combines synapses, which convert incoming spikes according to synaptic strength, with a neuron that integrates those currents and generates output spikes. Resistive-memory conductance can be adjusted through applied potential, enabling timing-dependent synaptic plasticity.
II. BRAIN-INSPIRED NEUROMORPHIC SYSTEM
- A basic neuromorphic unit combines synapses that convert incoming spikes according to synaptic strength with a neuron that integrates spiking pulses and generates output spikes.Dendrites and axons are modeled with interconnect circuits.Source: §II · pp. 1–2
- Resistive synapses convert voltage spikes into currents proportional to synaptic weights, which the neuron integrates to change membrane voltage and fire upon reaching threshold.Fig. 1C depicts this integrate-and-fire mechanism.Source: Figure 1 · p. 2
- STDP modulates synaptic weight according to the relative timing of pre- and post-synaptic spikes: repeated pre-before-post arrivals increase weight, while post-before-pre arrivals decrease it.The weight change Δw is plotted against relative spike timing Δt.Source: §II · p. 2
- Nanoscale resistive synapses and hardware in-situ learning make a versatile CMOS neuron that interfaces with resistive synapses a key component for large-scale neuromorphic systems.The passage identifies compact synaptic devices and hardware-friendly learning as longstanding challenges.Source: §II · p. 2
III. CMOS SPIKING NEURON ARCHITECTURE
The architecture addresses three barriers to using resistive synapses with silicon IFNs: STDP-compatible learning pulses, current integration and large-load driving, and avoiding area-consuming synapse accessory circuits. The proposed circuit centers on dual-mode operation and programmable spike generation.
III. CMOS SPIKING NEURON ARCHITECTURE
- Resistive-synapse IFNs face three challenges: in-situ learning, driving capability, and accessory circuits attached to synapses.The paper motivates an empirical IFN abstraction to support high parallelism within chip size and power budgets.Source: §III · p. 2
- Online learning requires synapse-compatible pulse shapes; digitally configurable amplitudes and widths support differing device thresholds and operating frequencies.The required STDP-compatible spikes also accommodate evolving spike-based learning algorithms.Source: §III · p. 2
- Conventional current-input IFNs cannot directly combine currents from 1MΩ-1GΩ synapses with driving thousands in parallel; an opamp-based IFN offers current summing and drive capability.The stated resistance range and load scale motivate the opamp architecture.Source: §III · p. 2
- The design seeks a single-wire synapse connection by placing current summing and pre-spike driving, and post-spike propagation and large-current driving, on shared nodes.The proposed circuit comprises an opamp, comparator, phase controller, spike generator, three switches, integration capacitor, and leaky resistor.Source: §III · p. 3
A. Event-driven Dual-mode Operation
A single opamp is reconfigured asynchronously as a leaky integrator during integration and as a voltage buffer during firing. This dual use supports current summing and bidirectional STDP spike driving through the synapse connections.
A. Event-driven Dual-mode Operation
- The single opamp is asynchronously reconfigured as an integrator during integration and as a resistive-load driver during firing.The circuit uses two asynchronous operating modes.Source: A. Event-driven Dual-mode Operation · p. 3
- In integration mode, the opamp sums injected currents and charges Cmem through a leaky-integrator configuration, changing Vmem until it crosses Vthr and triggers firing.Rleaky controls the leak rate; Vrefr sets the opamp common-mode voltage.Source: A. Event-driven Dual-mode Operation · p. 3
- During firing, the opamp becomes a voltage buffer that sends STDP spikes to pre- and post-synapses, then discharges Cmem by reconnecting it to Vrefr.Both synapse directions use the shared output node where currents are summed during integration.Source: A. Event-driven Dual-mode Operation · p. 3, Figure 3 · p. 3
- A dynamically biased class-AB output stage shuts off its main branch during integration and turns it on during firing to drive sharp-edged STDP spikes.Its rising and falling slew rates are 784/500 V/μs.Source: A. Event-driven Dual-mode Operation · p. 3, Figure 4 · p. 4
B. STDP-Compatible Spike Generation
The neuron generates tunable STDP-compatible spikes using a short positive pulse and a longer negative tail. Their timing and net potential govern resistive-synapse weight changes.
B. STDP-Compatible Spike Generation
- A short, large-amplitude positive pulse followed by a slowly decreasing negative tail provides a circuit-friendly shape for a similar STDP learning function.The positive pulse uses a selected voltage reference; the negative tail uses an RC discharging waveform.Source: B. STDP-Compatible Spike Generation · p. 4
- Digitally controlled voltage references and configurable capacitor and resistor banks tune spike amplitudes and transient response to resistive-synapse characteristics.The design targets variation in synapse thresholds and program/erase pulse shapes.Source: B. STDP-Compatible Spike Generation · p. 4
- The pre- and post-synaptic spikes create Vnet = Vpost – Vpre; crossing positive or negative thresholds decreases or increases synapse resistance, respectively.The caption specifies resistance reduction above Vt,p and increase below -Vt,m.Source: B. STDP-Compatible Spike Generation · p. 4, Figure 5 · p. 4
- A compact digital phase-control circuit generates non-overlapping Φint and Φfire signals that switch the IFN between its two operating modes; one-shot-generated Φ1 and Φ2 define positive- and negative-tail spike timing.Source: B. STDP-Compatible Spike Generation · p. 4
IV. MEASUREMENT RESULTS
Measurements on the fabricated chip demonstrate STDP-based associative learning and neuron operation under a load representing thousands of resistive synapses. The tests also characterize the chip and quantify the load and plasticity conditions.
IV. MEASUREMENT RESULTS
- The test chip was fabricated in 0.18 μm CMOS, with three neurons occupying 0.01 mm² each and three 8×8 on-chip tungsten electrode arrays.The chip also included configurable capacitor and resistor banks, biasing and voltage-reference circuitry, and a digital interface.Source: §IV · p. 4, Figure 6 · p. 4
- After paired stimulation strengthened the IFN2–IFN3 synapse, IFN2 alone excited IFN3, demonstrating an experimentally measured association.Before learning, IFN3 responded only to IFN1; the two input synapses began at 51 kΩ and 1 MΩ.Source: Figure 8 · p. 5, §IV · p. 5
- 9.3 pJ/spike/synapse was consumed for plasticity with 1,000 synapses, each around 1 MΩ; a Δt around 0.5 μs produced Vnet above Vt,p = 340 mV in a 0.4 μs window.The measured typical output spike was taken while driving 1 kΩ in parallel with 20 pF, equivalent to a few thousand nominal 1 MΩ synapses.Source: §IV · pp. 4–5, Figure 7 · p. 4
V. DISCUSSION
The discussion identifies resistive-device and scaled-VLSI challenges for large neuromorphic chips. The fabricated chip was primarily a neuron-architecture verification platform, leaving layout and power optimization open.
V. DISCUSSION
- Device variability, sneak paths, and crosstalk in nanoscale resistive devices can be detrimental to network-level learning.These effects are identified as challenges in current nanoscale devices.Source: §V · p. 5
- Large-scale brain-inspired chips must also account for interconnects, power distribution, and signal integrity.These are presented as conventional issues in scaled VLSI systems.Source: §V · p. 5
- Because the fabricated chip primarily verifies the neuron architecture across device types, its layout size and power remain open to optimization.Source: §V · p. 5
VI. CONCLUSIONS
The conclusion presents a compact CMOS leaky integrate-and-fire neuron for driving bare resistive synapses and in-situ STDP learning. Test-chip measurements verified its functionality, and an associative-learning experiment demonstrated learning without additional training circuitry.
VI. CONCLUSIONS
- The proposed compact spiking leaky integrate-and-fire neuron drives many bare resistive synapses and realizes in-situ STDP learning.Source: §VI · p. 5
- Measurements on a fabricated test chip in standard 0.18 μm CMOS verified the neuron's functionality.Source: §VI · p. 5
- An associative-learning experiment demonstrated in-situ learning without additional training circuitry.Source: §VI · p. 5