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Proposal for an All-Spin Artificial Neural Network: Emulating Neural and Synaptic Functionalities Through Domain Wall Motion in Ferromagnets

Abhronil Sengupta, Yong Shim, Kaushik Roy

arXiv:1510.00459v4cs.ET

TL;DR

Existing neuromorphic approaches have generally emphasized either synapses or neurons, motivating a unified low-power architecture. The paper proposes an All-Spin ANN in which one spintronic device performs both roles and CMOS transistors provide inter-layer communication. Simulations report approximately 100x energy savings versus a corresponding digital/analog CMOS neuron implementation, alongside about 80% accuracy on 260 images.

  • Problem

    Existing post-CMOS neuromorphic architectures have focused mainly on mimicking either synapses or neurons, limiting unified neural functionality.

  • Method

    The proposed All-Spin ANN uses a ferromagnet–heavy-metal spintronic device whose domain-wall-controlled conductance implements synapse and neuron functions, with CMOS transistors providing axon communication.

  • Results

    Simulation studies indicate approximately 100x energy savings versus a corresponding digital/analog CMOS neuron implementation, while network accuracy reached ∼80% on 260 images.

  • Takeaways & Limitations

    A single spintronic device can serve as the basic building block for an All-Spin neural architecture targeting ultra-low-power pattern recognition.

Abstract

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Non-Boolean computing based on emerging post-CMOS technologies can potentially pave the way for low-power neural computing platforms. However, existing work on such emerging neuromorphic architectures have either focused on solely mimicking the neuron, or the synapse functionality. While memristive devices have been proposed to emulate biological synapses, spintronic devices have proved to be efficient at performing the thresholding operation of the neuron at ultra-low currents. In this work, we propose an All-Spin Artificial Neural Network where a single spintronic device acts as the basic building block of the system. The device offers a direct mapping to synapse and neuron functionalities in the brain while inter-layer network communication is accomplished via CMOS transistors. To the best of our knowledge, this is the first demonstration of a neural architecture where a single nanoelectronic device is able to mimic both neurons and synapses. The ultra-low voltage operation of low resistance magneto-metallic neurons enables the low-voltage operation of the array of spintronic synapses, thereby leading to ultra-low power neural architectures. Device-level simulations, calibrated to experimental results, was used to drive the circuit and system level simulations of the neural network for a standard pattern recognition problem. Simulation studies indicate energy savings by ~ 100x in comparison to a corresponding digital/ analog CMOS neuron implementation.

I. INTRODUCTION

The paper motivates an All-Spin neural architecture because conventional and existing post-CMOS approaches separately address neural functions, while spintronic devices offer low-voltage thresholding and potentially unified neuron–synapse operation.

  • I. INTRODUCTION: Conventional von Neumann, analog CMOS, and digital CMOS implementations are respectively energy inefficient, power-hungry, or area-expensive for neural computation.These limitations arise from their poor direct mapping to weighted summation and thresholding.
  • I. INTRODUCTION: Emerging devices such as PCMs and memristors directly mimic synapses, but their systems still require analog CMOS neurons.The passage notes that synapses outnumber neurons by several orders of magnitude.
  • I. INTRODUCTION: Spintronic neurons provide direct, ultra-low-voltage and ultra-low-current mappings to neural thresholding, but prior designs primarily implemented step transfer functions.Linear or sigmoid transfer functions can encode more information for complex pattern recognition tasks.
  • I. INTRODUCTION: The proposed All-Spin architecture uses one ferromagnet–heavy-metal spintronic device for both neuron and synapse functionalities, with CMOS axon transistors connecting layers.The device is intended to provide a non-step transfer function for complex pattern recognition.

II. SPINTRONIC DEVICE STRUCTURE: PRINCIPLE OF OPERATION

The proposed three-terminal MTJ uses domain-wall motion in a ferromagnet to encode state, with separate write and read paths enabling spintronic neuron and synapse operation. Spin-orbit torque from a heavy-metal underlayer displaces the wall, while calibrated device simulations model its electrical behavior.

  • The basic building block is an MTJ whose free and pinned ferromagnetic layers are separated by an MgO tunnel barrier, with a domain wall in the free layer.
  • Spin-orbit torque from charge current in the heavy-metal underlayer displaces the domain wall, with DMI stabilizing a chiral Néel wall in the ferromagnet.
  • The proposed device decouples write and read paths: Iwrite programs domain-wall position through the heavy metal, while Iread senses MTJ conductance.
  • The read current must remain below the minimum current that depins the domain wall, preserving the programmed state during sensing.
  • NEGF transport simulations model MTJ resistance as a function of MgO thickness, magnetization angle, and applied voltage, calibrated against experimental data.

A. Synapse Functionality

The device implements synaptic weighting by storing domain-wall position and converting it into a programmable conductance. Applied synapse voltage therefore produces a current scaled by the stored conductance.

  • The spintronic device acts as a synapse by storing a weight through the domain-wall position in its free layer.
  • The equivalent conductance GS varies linearly with domain-wall position x because the parallel, antiparallel, and domain-wall conductances remain constant at fixed read voltage.
  • Programming the domain-wall position sets the synaptic conductance, so an applied voltage VS generates a modulated current IS = GS.VS.
  • ∼600% TMR corresponds to a maximum-to-minimum synaptic weight ratio of ∼7× in the MTJ.

B. Neuron Functionality

The proposed device operates as a neuron by receiving the resultant synaptic current and producing an output through staged write, read, and reset operations.

  • The neuron operation comprises three stages: write, read, and reset.
  • During the write stage, the neuron receives the resultant synaptic input current at its input terminals.

C. Correspondence to Biological Neural Network

The proposed All-Spin network maps biological synapses, neurons, and axons onto spintronic devices and CMOS interconnects. Weighted synaptic current drives the spintronic neuron, whose output is transmitted to the next stage.

  • Spintronic synapses provide weighted inputs whose summed current drives the spintronic neuron.
  • The spintronic neuron converts resultant synaptic current into an output transmitted through a CMOS transistor acting as the axon.

IV. ALL-SPIN NEUROMORPHIC ARCHITECTURE

The All-Spin architecture implements feedforward ANN layers with crossbar synapses, domain-wall-encoded conductances, spintronic neurons, and CMOS axon transistors. Low neuron voltage supports low-voltage array operation, while scalability depends on current-driving capability and array organization.

  • A resistive crossbar applies input voltages across spintronic synapses whose domain-wall positions encode synaptic conductances.The crossbar columns connect to spintronic neurons.
  • The resultant synaptic current is formed by equating current through the resistive synapses with current through the neuron.
  • Less than ∼10mV neuron terminal voltage enables ultra-low-voltage operation of the crossbar array.The operating voltage is kept to a few tens of mV so synaptic resistance remains relatively stable with applied voltage.
  • PMOS axon transistors drive equivalent conductances in the succeeding layer during output-layer operation.
  • Positive and negative synaptic weights are implemented with separate crossbar arrays operated in two write cycles.
  • Scalability is constrained by the driving capability of neurons and synapses as synaptic-input count increases.Large arrays can be distributed across smaller crossbar arrays to address transistor current limits.
  • The resistance range of the synapses is constrained by the architecture’s operating conditions.

V. SIMULATION FRAMEWORK AND RESULTS

The study evaluates the All-Spin neural network using a hybrid device–circuit–algorithm co-simulation framework. The framework combines top-down and bottom-up perspectives.

  • A hybrid device–circuit–algorithm co-simulation framework assesses the proposed network’s functionality and power consumption.The framework uses complementary top-down and bottom-up perspectives.

A. Top-Down Perspective

A small All-Spin ANN was simulated for character recognition using device-derived transfer behavior and learned synaptic weights. It achieved approximately 80% accuracy on 260 Chars74K images.

  • 20 hidden neurons and 26 output neurons recognized characters A–Z from downscaled 16x16 Chars74K images.The input images were presented as one-dimensional vectors.
  • The neuron transfer function increased linearly with input before saturating at a maximum value.This transfer function was obtained from device- and circuit-level simulations.

B. Bottom-Up Perspective

The bottom-up framework combines experimentally calibrated device physics, micromagnetic domain-wall simulations, and NEGF transport modeling to characterize the proposed spintronic device.

  • B. Bottom-Up Perspective: The simulation framework investigates current-induced spin-orbit torque and develops behavioral models for system-level All-Spin neural-network simulations.Parameters were obtained experimentally from Ta(3nm)/Pt(3nm)/CoFe(0.6nm)/MgO(1.8nm)/Ta(2nm) nanostrips.
  • B. Bottom-Up Perspective: 25µA for 1ns displaces the domain wall across a 120nm ferromagnetic layer bounded by 20nm pinned regions.The programming current flows through the heavy-metal underlayer.
  • B. Bottom-Up Perspective: The micromagnetic model shows domain-wall velocity increasing linearly with current density before reaching saturation, consistent with prior experimental results.The simulations used MuMax3 and modeled a DMI-stabilized domain wall in a ferromagnet-heavy-metal structure.
  • B. Bottom-Up Perspective: The NEGF transport framework models MTJ resistance as a function of oxide thickness, magnetization configuration, and applied voltage, calibrated against experimental results.A domain-wall-containing free layer is represented using a parallel connection of three MTJs with different magnetization orientations.

C. System Level Simulations

System-level simulations evaluate discretization, operating points, axon-transistor transfer, variability tolerance, and energy consumption for the All-Spin neural network. The results support low-voltage operation and robust classification under modeled device variation.

  • C. System Level Simulations: 15 intermediate synapse-weight levels and 3 intermediate neuron-output levels caused insignificant accuracy degradation on the image set.The assumed 10nm sensing distance and approximately 10nm domain-wall width led to 50nm neuron and 170nm synapse free layers.
  • C. System Level Simulations: ∼5µA displaces the neuron domain wall across its 50nm free layer in 2ns, while system simulations provide ∼50µA maximum synaptic current and ∼7mV maximum neuron voltage drop.The estimated resistance in the synaptic-current path is ∼140Ω.
  • C. System Level Simulations: 100mV across each crossbar row produces ∼5µA through the minimum 20KΩ synaptic resistance while keeping read-current-induced domain-wall motion negligible.MTJ resistance variation with applied voltage was considered insignificant below 100mV.
  • C. System Level Simulations: The axon transistor output current increases almost linearly with the neuron input current and is sized to maintain ∼100mV across the crossbar array.Its gate voltage decreases as neuron input-current magnitude increases.
  • C. System Level Simulations: < 4% classification-accuracy degradation was observed with 20% 3σ resistance variation across 100 stochastic network simulations.The paper attributes this tolerance to the error-resilient nature of brain-inspired computing systems.
  • C. System Level Simulations: 0.17fJ average write energy and 0.15fJ read energy were estimated for the simulated network neuron operation.The energy analysis used an average neuron current of ∼17.5µA over a 4ns evaluation window and ∼80nA read current.
  • C. System Level Simulations: The All-Spin architecture uses a single nanoelectronic device to mimic neuron and synapse functionalities and is evaluated on a standard image-recognition problem.The paper presents the architecture as a potential route toward ultra-low-power deep-learning neural systems.
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