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qHiPSTER: The Quantum High Performance Software Testing Environment
Mikhail Smelyanskiy, Nicolas P. D. Sawaya, Alán Aspuru-Guzik
TL;DR
Generic quantum circuits are expensive to simulate classically because their state vectors grow exponentially with the number of qubits. qHiPSTER implements distributed, optimized simulation of general single-qubit and controlled two-qubit gates. On 1024 Stampede nodes, it simulates circuits up to 40 qubits, including a 40-qubit QFT in 997 seconds, while network contention limits performance for high-order gates.
Problem
Generic quantum-circuit simulation is inefficient because n qubits require 2^n complex amplitudes, creating exponential memory and runtime demands.
Method
qHiPSTER is a distributed classical quantum simulator using gate-operation optimizations and overlapping computation with communication.
Results
Using 1024 Stampede nodes, qHiPSTER simulates circuits up to 40 qubits and completes a 40-qubit quantum Fourier transform in 997 seconds.
Takeaways & Limitations
Cache blocking reduces gate-operation runtime by approximately 2.56×, while communication-required operations become network-bandwidth bound and take roughly 10× longer.
Takeaways & Limitations
Network contention on low-diameter multilevel networks limits simulator performance when high-order gates communicate across longer strides.
Abstract
from arXiv · showhide
We present qHiPSTER, the Quantum High Performance Software Testing Environment. qHiPSTER is a distributed high-performance implementation of a quantum simulator on a classical computer, that can simulate general single-qubit gates and two-qubit controlled gates. We perform a number of single- and multi-node optimizations, including vectorization, multi-threading, cache blocking, as well as overlapping computation with communication. Using the TACC Stampede supercomputer, we simulate quantum circuits ("quantum software") of up to 40 qubits. We carry out a detailed performance analysis to show that our simulator achieves both high performance and high hardware efficiency, limited only by the sustainable memory and network bandwidth of the machine.
1. INTRODUCTION
Quantum simulation helps evaluate algorithms and circuits, but generic circuits incur exponential state-vector costs that constrain classical simulation. qHiPSTER addresses these limits with distributed high-performance computing and simulates circuits up to 40 qubits on Stampede.
- Classical simulation supports validating quantum-algorithm complexity, studying analytically difficult circuits, and evaluating circuits under noise.
- Quantum-circuit design involves alternative qubit mappings, gate sequences, and noise models whose performance and resource effects can be studied with high-performance simulation.
- Generic quantum-circuit simulation requires exponential resources because n qubits need 2^n complex amplitudes in the state vector.
- Memory capacity limits simulated system size, while circuit gate counts can impose substantial classical runtime requirements.
- Most single-CPU simulators are limited to approximately 30–33 qubits, motivating distributed systems with larger aggregate memory capacity.
- Using 1024 Stampede nodes, qHiPSTER simulates circuits up to 40 qubits and completes a 40-qubit quantum Fourier transform in 997 seconds.
2. BACKGROUND
qHiPSTER represents quantum computation with state vectors and applies universal single-qubit and controlled two-qubit gates directly to amplitude pairs. The target qubit determines the memory stride, creating implementation challenges for higher-order qubits.
- qHiPSTER propagates pure states using a 2^N × 1 state vector rather than a 2^N × 2^N density matrix.
- The simulator focuses on general single-qubit and controlled-Q gates, including controlled-NOT, which are universal gate types.
- A single-qubit gate applies a 2×2 unitary matrix Q directly to amplitude pairs instead of constructing the full system transformation U.
- Amplitude indices use binary representations, and applying a gate to qubit k pairs amplitudes whose indices differ in the k-th bit.
- The stride between paired amplitudes is 2^k, so gates on high-order qubits create large strides that challenge single- and distributed-node implementations.
- A controlled-Q gate applies Q to the target only when the control qubit is |1⟩; otherwise, the target remains unchanged.
3. IMPLEMENTATION
qHiPSTER implements gate updates by iterating over amplitude pairs, then distributes state vectors across nodes when target pairs span processors. The distributed design uses processor exchanges and temporary storage to perform these updates.
- 3.1 Single node implementation: The single-node kernel iterates through amplitude groups and applies Q to pairs separated by stride 2^k.
- 3.2 Distributed implementation: Distributed single-qubit updates exchange state halves between processor pairs, compute using temporary storage, and exchange data again.
- 3.1 Single node implementation: Controlled-Q uses an additional outer loop to skip amplitudes whose control-qubit bit is zero.
- 3.2 Distributed implementation: The distributed state vector is divided across 2^p nodes, with each node storing 2^(n−p) amplitudes and requiring sufficient local memory.
- 3.2 Distributed implementation: For a gate on qubit k, communication is unnecessary when k < m; when k ≥ m, paired amplitudes reside on different nodes separated by virtual distance 2^(k−m).
- 3.2 Distributed implementation: Controlled gates require four distributed cases based on whether the target and control qubits are local or remote.
4. ARCHITECTURALANDALGORITHMIC OPTIMIZATION
qHiPSTER combines CPU, cache, threading, and distributed-memory optimizations to accelerate single- and multi-node quantum-gate simulation. Its multistep distributed design reduces temporary storage and can overlap communication with computation, while gate fusion keeps working data in the LLC.
- Single-node optimizations: SIMD maps data-parallel gate-loop iterations onto 4-wide AVX2 instructions for simultaneous double-precision processing.Two inner-loop iterations are mapped to four SIMD register entries because each complex number has real and imaginary parts.
- Single-node optimizations: Multithreading parallelizes both inner- and outer-loop work, with the balance changing according to the operated qubit’s index.The outer loop has 2^(n-k-1) iterations and the inner loop has 2^k iterations.
- Improvement in communication: 31 qubits become simulable on a 48GB node by reducing temporary storage from 16GB to 8GB through multistep distributed exchange.The two-step approach reuses temporary storage and adds one qubit over the original 30-qubit practical limit.
- Improvement in communication: Overlapping computation with communication changes distributed runtime from Ttot = Tcomp + Tcomm to Ttot = max(Tcomp, Tcomm).The multistep schedule overlaps computation and communication across neighboring exchange steps, partially hiding communication overhead.
- Cache blocking through gate fusion: Gate fusion blocks computation in the LLC by applying consecutive gates to blocks of 2^lc amplitudes that remain cache-resident.This restructuring exploits the LLC’s higher bandwidth than main memory.
5. PERFORMANCE
qHiPSTER achieves near-bandwidth-bound performance for local quantum-gate operations, while communication, network contention, and qubit placement constrain distributed performance. Optimizations and scaling experiments demonstrate simulation of systems up to 40 qubits on Stampede.
- 1000 nodes with 32 Tbytes of aggregate memory enabled qHiPSTER to simulate quantum systems of up to 40 qubits.
- Fusion reaches 100 GB/s per gate at 21 qubits and 70 GB/s at 29 qubits, improving performance by almost 2.5× over no fusion.
- 4× speedup across four sockets occurs for gates on qubits 15–26 without communication, whereas communicating gates incur a 2× slowdown.
- Weak scaling keeps local state size fixed, but higher-qubit gates become slower because multi-level network topology and job interference increase contention.
- QFT runtime rises from 116 seconds at 29 qubits to 997 seconds at 40 qubits, allowing approximately 86 40-qubit QFT calls within a 24-hour limit.
6. FUTURE DIRECTIONS
Future work is constrained by exponentially growing state-vector memory requirements and network contention, while communication-avoiding techniques may extend simulations beyond 49 qubits.
- 49 qubits is identified as the practical near-term limit for general-purpose circuit simulation because storing the entire state vector requires exponentially increasing memory.The stated limit applies to the next six years and cannot be overcome for general-purpose simulations under this storage model.
- High-bandwidth memory may improve simulator performance, with upcoming systems offering up to 16GB capacity and over 400GB/s bandwidth.The passage contrasts high-bandwidth memory with traditional DRAM and notes its adoption in commercial systems.
- Network contention limits performance when high-order-qubit operations communicate across longer strides on low-diameter multilevel networks such as dragonfly.These operations can congest global links between communicating processors.
- Communication-avoiding methods combine cache blocking with state reordering to reduce memory traffic and avoid inter-node communication.State reordering makes high-order communicating qubits low-order, but must balance additional reordering overhead against increased opportunities.
- State reordering could eventually support storing the state vector on higher-capacity secondary devices and enable simulations beyond 49 qubits in principle.The passage identifies minimizing transfers between secondary storage and main memory as a remaining challenge.