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Basic circuit compilation techniques for an ion-trap quantum machine

Dmitri Maslov

arXiv:1603.07678v4quant-phcs.ET

TL;DR

Quantum algorithms need efficient physical-level implementations, but implementable gate sequences depend on the QIP platform. The paper develops a trapped-ion compilation and optimization strategy; its QFT5 design uses fewer single-qubit gates than the cited comparison while retaining the same two-qubit gate count.

  • Problem

    Composing efficient physical-level gate sequences from quantum algorithms depends on which gates a QIP platform can implement.

    Source: §1 · p. 2

  • Method

    The paper develops a multistage compiler and combines gate decompositions with circuit-cost optimization for trapped-ion experiments.

    Source: §1 · p. 2, §6 · p. 16

  • Results

    22 single-qubit gates versus 70 in [6], with both true QFT5 circuits using 10 two-qubit gates.

    Source: §5.2 · p. 16

  • Takeaways & Limitations

    The strategy produces optimized computational experiments designed for execution on the specific machine available in the lab.

    Source: §6 · p. 16

    The paper does not aim to provide a complete experimental error model and selects e1 for optimization.

    Source: §2.1.1 · p. 3

Abstract

from arXiv · show

We study the problem of compilation of quantum algorithms into optimized physical-level circuits executable in a quantum information processing (QIP) experiment based on trapped atomic ions. We report a complete strategy: starting with an algorithm in the form of a quantum computer program, we compile it into a high-level logical circuit that goes through multiple stages of decomposition into progressively lower-level circuits until we reach the physical execution-level specification. We skip the fault-tolerance layer, as it is not within the scope of this work. The different stages are structured so as to best assist with the overall optimization while taking into account numerous optimization criteria, including minimizing the number of expensive two-qubit gates, minimizing the number of less expensive single-qubit gates, optimizing the runtime, minimizing the overall circuit error, and optimizing classical control sequences. Our approach allows a trade-off between circuit runtime and quantum error, as well as to accommodate future changes in the optimization criteria that may likely arise as a result of the anticipated improvements in the physical-level control of the experiment.

1 Introduction

The paper describes a trapped-ion platform and presents a compiler strategy that maps logical quantum circuits into optimized physical experiments. Its motivation is to make increasingly large quantum circuits practical on available hardware.

1 Introduction

  • Trapped-ion qubits are stored in ion spins, and laser-driven R and XX gates form a universal physical-level library with selectable qubit pairs.The cited experiment reports average CNOT fidelity of 95.6 −98.5%, depending on the qubit pair; CNOT is composite from native gates.Source: §1 · pp. 1–2
  • With circuits of dozens of physical gates within reach, circuit optimization becomes crucial to their realization.The cited QFT5 experiment used 80 physical single- and two-qubit gates.Source: §1 · p. 2
  • The proposed workflow decomposes algorithms into lower-level circuits and maps logical circuits to physical experiments, alongside gate designs and circuit-cost optimization.With full qubit connectivity, SWAP gates can be moved to the circuit end and implemented classically at no quantum-computation cost.Source: §1 · p. 2

2 Single-Qubit Gates

This section develops physical-level single-qubit rotations and cost-aware decompositions for common and arbitrary gates. It models runtime and error to guide circuit optimization.

2.1 Physical-level single-qubit rotation

  • The controlling apparatus sets the R(θ, φ) rotation through the duration and phase of the Raman beatnote.These parameters control the rotation angle and phase.Source: §2.1 · p. 2

2.1.1 Single-qubit gate cost

  • The cost vector (d, e) tracks runtime and modeled error; e1 and e2 represent pulse-area fluctuation errors, and the authors select e1 because optimizing e2 is equivalent to optimizing duration.The authors state that complete experimental error modeling is outside the paper's focus.Source: §2.1.1 · p. 3

2.2 The RX, RY, and RZ rotations

  • Selectable RY signs enable gate cancellations; commuting RX(π) around XX can reduce an internal RZ to one physical R gate.The physical R rotation's angle and phase are controlled through Raman beatnote duration and phase.Source: §2.1 · p. 2, §2.2 · pp. 4–5

2.3 Other common single-qubit rotations

  • Hadamard costs (1.5τ1q, ϵ), roughly like RZ and more than RX or RY; choosing RX/RY order supports circuit optimization.The alternative orderings are part of the Hadamard decompositions discussed in this subsection.Source: §2.3 · p. 5

2.4 Arbitrary single-qubit rotations

  • Any arbitrary single-qubit unitary can use a minimal two physical R gates; circuits with n qubits and G XX gates need at most 2(n + 2G) R gates.For QFT5, the lemma gives an upper bound of 60 total gates, showing the cited 80-gate circuit is suboptimal.Source: §2.4 · p. 6

3 Two-Qubit Gates

The paper builds trapped-ion circuits from the available XX interaction and single-qubit gates, choosing decompositions to reduce costly two-qubit operations and balance runtime against error. It gives compact constructions for CNOT and controlled Pauli roots, then uses circuit identities to enable further cancellation and optimization.

3.1 Physical-level two-qubit gate

  • The physical XX(χ) interaction has a pair-dependent sign that is fixed experimentally, while its absolute angle can be varied from 0 to π/2.XX(χ) commutes with RX rotations but not with RY or RZ rotations.Source: §3.1 · pp. 6–7

3.1.1 Cost function variables

  • Because XX gates are serial, longer, and higher-error than single-qubit R gates, the cost model prioritizes reducing their use.The two-qubit cost pairs duration with an error model that can depend on the interaction angle or use a constant error value.Source: §3.1.1 · p. 7

3.2 Constructing the CNOT gate

  • The CNOT construction uses the fixed interaction sign and an arbitrary RY sign choice, and costs 2τ1q + τ2q with error 4 × ϵ + 1 × E.The chosen RY signs can support cancellations when decomposing logical circuits with multiple CNOT gates.Source: §3.2 · p. 7
  • The CNOT decomposition uses two fewer single-qubit pulses than the implementation reported in [6], with selectable RY signs that permit cancellations.The selectable sign can set the first RY rotation to +π/2 or place the positive sign on the second rotation instead.Source: §3.2 · p. 7

3.3 Constructing controlled-roots of Paulis

  • Every controlled root of a Pauli gate can be implemented with at most one physical-level XX gate.This improves by a factor of two over using two CNOT or Mølmer–Sørensen gates for a controlled unitary.Source: §3.3 · p. 8

3.4 Useful single-qubit circuit identity

  • The single-qubit template replaces RX(a)RY(b)RX(a) with R(c, d), reducing duration while increasing fidelity; related rewrites can trade runtime for error.Commuting RX rotations through RY gates using the template can reduce the RX count to at most one per qubit without increasing the XX count.Source: §3.4 · p. 10

4 Compiling quantum algorithms into physical-level circuits

The compilation strategy maps a quantum algorithm through successive logical and physical-level circuits, using coarse-grain and fine-grain costs at different stages. It combines gate decomposition, qubit mapping, and physical-level optimization to balance two-qubit gate use, runtime, and error.

Cost metrics and optimization

  • The approach defines coarse-grain cost by controlled Pauli-root count and fine-grain cost by total time and combined error.If control hardware supports parallel gates, runtime can instead be measured along the critical path; the metrics may be adjusted as hardware and error models change.Source: §4 · p. 11

Compilation stages 2–4

  • The pipeline first synthesizes arithmetic, oracles, and multi-control gates, then decomposes gates into controlled Pauli roots and single-qubit gates while optimizing coarse-grain cost.After this stage, the approach switches to fine-grain costs because it considers the number of most expensive two-qubit gates optimized.Source: §4 · p. 11

Compilation stage 5

  • Physical-qubit mapping seeks to avoid the least-fidelitous XX interactions and maximize RY cancellations between control qubits.The mapping can be exhaustive for small qubit counts; larger cases can use subgraph-isomorphism and greedy heuristics.Source: §4 · p. 11

Compilation stage 6

  • The final physical-level optimization applies decompositions and cancellations, then uses single-qubit templates to improve the selected cost figure of merit.Template rewrites can trade runtime against error; remaining long single-qubit sequences are shortened before RX and RY gates are rewritten as physical R pulses.Source: §4 · pp. 11–12

Overall design approach

  • The main new optimization work lies in stages 5 and 6, whose algorithms have low-degree polynomial complexity in gate count in the simplest cases.Stage 5 complexity depends on the heuristics used, while stages 1–4 adapt and combine known techniques.Source: §4 · p. 12

5 Benchmark results

The paper applies its trapped-ion compilation and optimization methods to a Boolean multiplication circuit and proposed advanced experiments. The designs reduce gate counts in selected circuits, while the benchmark targets a specific machine and its physical-error constraints.

5 Benchmark results

  • The machine has approximate single- and two-qubit gate errors of 0.01 and 0.04, respectively, leading the authors to target circuits with about 15 or fewer two-qubit gates.The two-qubit error can vary slightly with the qubit pair.Source: §5 · p. 12
  • For a CNOT, the paper reports 1 XX gate and 4 single-qubit pulses, compared with 2 XX gates and 8 single-qubit pulses in [22]; the implementations use different physical-level gates.The authors say a direct comparison cannot be made and expect their optimization algorithms to be more computationally efficient than gradient-ascent techniques.Source: §5 · p. 12

5.1 Implementing Boolean multiplication

  • The Boolean multiplication design reduces the single-qubit pulse count from 20 to 9 using the parametrized CNOT implementation, joint decomposition, and RX commutation.With the previously known CNOT implementation, the unoptimized count would have been 30; without the efficient controlled-root-of-Pauli implementation, both single- and two-qubit resource counts would be substantially higher.Source: §5.1 · p. 14
  • The reported Toffoli implementation takes 1285 µs versus 1500 µs in [24], but the duration advantage is attributed to different hardware.The fidelity difference requires experimental comparison; the paper distinguishes its true Toffoli from the relative-phase implementation in [24].Source: §5.1 · pp. 14–15

5.2 Advanced experiments

  • A single Grover iterate for a three-bit function marking two items uses 16 two-qubit gates and has algorithmic success probability 0.78125, versus 0.125 for a single classical query.The oracle is treated as a black box, with no optimization across its boundary.Source: §5.2 · pp. 15–16
  • For a 2-out-of-8 phase-oracle search, the proposed circuits use 6–8 two-qubit XX gates; a 1-out-of-8 search uses 10.Some four-qubit phase-oracle searches are also proposed, including one using 16 XX gates.Source: §5.2 · p. 16
  • 22 single-qubit gates versus 70 in [6] for true 5-qubit QFT circuits, both using 10 two-qubit gates.The authors attribute the reduction to careful circuit design.Source: §5.2 · p. 16
  • The proposed Toffoli-4 circuit uses no more than 11 two-qubit gates, compared with the previous best of 12 CNOTs [20].The authors describe it as the first such circuit with no more than 11 two-qubit gates.Source: §5.2 · p. 16

6 Conclusion

The paper concludes that it provides an end-to-end strategy for automatically executing quantum algorithms on a trapped-ion machine. It presents the optimization techniques as adaptable beyond the specific gate library used.

6 Conclusion

  • The strategy connects algorithm-level programs to physical-level execution through a complete data flow and circuit-cost optimization.Its contributions include gate decompositions, cancellation-based and single-qubit optimization, and physical-level designs of logical gates and computational primitives.Source: §6 · p. 16
  • The authors designed optimized computational experiments for execution on a specific laboratory machine using its R and XX physical controls.The paper describes these designs as computational primitives suitable for a range of QIP proposals.Source: §6 · p. 16
  • The approach is presented as a way to automatically design and execute quantum algorithms on existing hardware, bridging quantum experiments and a fully-fledged quantum computer.Source: §6 · p. 16
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