Integrating MEMS and ICs

Andreas C. Fischer; Fredrik Forsberg; Martin Lapisa; Simon J. Bleiker; Goran Stemme; Niclas Roxhed; Frank Niklaus

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Integrating MEMS and ICs

Andreas C. Fischer, Fredrik Forsberg, Martin Lapisa, Simon J. Bleiker, Goran Stemme, Niclas Roxhed, Frank Niklaus

arXiv:1604.04843v1Apr 17, 2016cond-mat.mtrl-sci

TL;DR

MEMS devices generally require ICs to condition, process, and communicate their transducer signals, but integration choices vary with device and product requirements. This review categorizes hybrid multi-chip and SoC technologies, compares their trade-offs, and examines their effects on packaging, testing, and system cost. It concludes that both approaches are moving toward denser, smaller, cheaper systems with more integrated sensing and signal processing, while specific methods retain important manufacturing and business-model constraints.

Problem
MEMS transducers typically need ICs for signal conversion, amplification, filtering, processing, and communication, making the choice among integration technologies important for complete products.
Method
The paper reviews, analyzes, and categorizes hybrid multi-chip and SoC integration technologies, including monolithic and heterogeneous wafer-level approaches, and examines their implementations and system-level implications.
Results
The review identifies distinct trade-offs: multi-chip solutions offer flexibility and lower complexity, whereas SoC solutions can reduce packaging and testing costs and support dense integration.
Takeaways & Limitations
Future multi-chip and SoC developments are converging toward higher integration densities, smaller and cheaper components, and modules combining multiple sensing and signal-processing functions.
Takeaways & Limitations
MEMS-first integration requires strict wafer planarity and material-exposure control, is generally unsuitable for standard CMOS fabs and fabless business models, and requires dedicated CMOS-fab access.

Abstract

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The majority of microelectromechanical system (MEMS) devices must be combined with integrated circuits (ICs) for operation in larger electronic systems. While MEMS transducers sense or control physical, optical or chemical quantities, ICs typically provide functionalities related to the signals of these transducers, such as analog-to-digital conversion, amplification, filtering and information processing as well as communication between the MEMS transducer and the outside world. Thus, the vast majority of commercial MEMS products, such as accelerometers, gyroscopes and micro-mirror arrays, are integrated and packaged together with ICs. There are a variety of possible methods of integrating and packaging MEMS and IC components, and the technology of choice strongly depends on the device, the field of application and the commercial requirements. In this review paper, traditional as well as innovative and emerging approaches to MEMS and IC integration are reviewed. These include approaches based on the hybrid integration of multiple chips (multi-chip solutions) as well as system-on-chip solutions based on wafer-level monolithic integration and heterogeneous integration techniques. These are important technological building blocks for the More-Than-Moore paradigm described in the International Technology Roadmap for Semiconductors. In this paper, the various approaches are categorized in a coherent manner, their merits are discussed, and suitable application areas and implementations are critically investigated. The implications of the different MEMS and IC integration approaches for packaging, testing and final system costs are reviewed.

1 INTRODUCTION

MEMS and ICs can be combined either as separate chips integrated in a hybrid multi-chip system or on the same substrate in a system-on-chip solution. This review compares these approaches, their implementations, and their implications for applications, packaging, testing, and cost.

MEMS transducers sense or control physical, optical, or chemical quantities, while ICs process their electrical signals and communicate with the outside world.
Multi-chip solutions manufacture MEMS and IC components on separate substrates before hybridizing them in the final system.
SoC solutions manufacture MEMS and IC components on the same substrate using consecutive or interlaced processing schemes.
Approximately half of existing MEMS products by market value use multi-chip solutions and the other half use SoC solutions.
The review provides an up-to-date comparison of established and emerging integration technologies and discusses their implementation in MEMS products.

2 HYBRID INTEGRATION OF MEMS AND ICS: MULTI-CHIP SOLUTIONS

Hybrid multi-chip integration keeps MEMS and IC fabrication separate, enabling modularity and flexibility across 2D, stacked, chip-scale, and package-level implementations. Three-dimensional and wafer-level variants reduce footprint and interconnect parasitics while retaining hybrid integration benefits.

2D multi-chip modules place independently fabricated MEMS and IC chips side-by-side and connect them at the board or package level.
Multi-chip modules shorten signal paths and reduce PCB area compared with system-on-board approaches, supporting integration with standard ASICs.
3D-stacked multi-chip approaches increase integration density and reduce signal path length and package footprint compared with side-by-side modules.
Chip-scale and wafer-scale packages achieve footprints similar to the largest chip, while through-substrate vias reduce capacitive, resistive, and inductive parasitic effects.
Package-level system-on-package designs can 3D-integrate MEMS, ASIC, wireless communication, and power-management components into complete sensor nodes.
Multi-chip solutions provide modularity, flexibility, low fabrication complexity, rapid development, and compatibility with different MEMS and IC chip sizes.

3 WAFER-LEVEL INTEGRATION OF MEMS AND ICS: SOC SOLUTIONS

SoC solutions fabricate MEMS and IC components on a common substrate, with separation occurring near the end of fabrication. They comprise monolithic and heterogeneous integration schemes.

SoC solutions integrate MEMS and IC components on the same substrate and separate chips only at or near the end of fabrication.
SoC integration divides into monolithic techniques, which fabricate MEMS and IC structures entirely on one substrate, and heterogeneous techniques, which use separately prefabricated structures.

3.1 SoC solutions using monolithic MEMS and IC integration

Monolithic MEMS–IC integration uses four processing strategies that place MEMS and CMOS on one substrate. Their trade-offs span thermal budget, material and design freedom, integration density, fab compatibility, and commercial applicability.

3.1 SoC solutions using monolithic MEMS and IC integration: Four SoC approaches are distinguished: MEMS-first, interleaved processing, MEMS-last bulk micromachining, and MEMS-last layer deposition with surface micromachining.These approaches differ in when MEMS processing occurs relative to CMOS fabrication and in whether structures are etched from or deposited onto the IC substrate.
3.1.1 Monolithic MEMS and IC integration using MEMS-first processing: MEMS-first processing completes the MEMS device before CMOS, allowing a thermal budget above 1100 °C and supporting high-performance materials and sealed structures.Planarization typically prepares the wafer for subsequent CMOS integration.
3.1.1 Monolithic MEMS and IC integration using MEMS-first processing: Bosch’s APSM process forms porous-silicon cavities by anodic HF etching, sintering, and epitaxial silicon growth, producing a membrane and CMOS-compatible surface.Related platforms fabricate MEMS in an SOI device layer and CMOS in an epitaxially grown silicon top layer, with HF vapor release in the SiTime–Stanford variant.
3.1.1 Monolithic MEMS and IC integration using MEMS-first processing: The plug-up process etches buried oxide through small holes, seals the holes with polysilicon, planarizes the surface by CMP, and then enables CMOS integration.Interleaved platforms similarly combine MEMS and CMOS steps around planarization and release, including shallow-trench M3EMS structures completed with post-CMOS HF etching.
3.1.1 Monolithic MEMS and IC integration using MEMS-first processing: MEMS-first and interleaved approaches can integrate high-performance MEMS with CMOS, but require stringent wafer planarity and access to dedicated custom CMOS lines, limiting fabless use.Interleaved processing also commonly places MEMS and CMOS side-by-side, constraining integration density.
3.1.3 Monolithic MEMS and IC integration using MEMS-last processing via the bulk micromachining of the IC substrate: MEMS-last bulk micromachining uses existing IC infrastructure and simple post-CMOS processing for potentially low-cost, rapid-development devices, but restricts MEMS materials and design freedom.Reliability and repeatability can suffer when CMOS production lines poorly characterize or control mechanical material properties.
3.1.4 Monolithic MEMS and IC integration using MEMS-last processing via layer deposition and surface micromachining: MEMS-last layer-deposition integration implements the vast majority of commercial micro-mirror arrays and uncooled infrared bolometer focal-plane arrays as SoC devices.Texas Instruments digital micro-mirror arrays are cited as an example.
3.1.4 Monolithic MEMS and IC integration using MEMS-last processing via layer deposition and surface micromachining: MEMS-last layer deposition and surface micromachining supports standard CMOS foundries, efficient area reuse, and extremely high density, but imposes deposition temperatures typically below 400 or 450 °C.This temperature constraint excludes important high-performance materials such as monocrystalline and poly-crystalline silicon, making the approach less attractive for some inertial sensors and resonators.

3.2 SoC solutions using heterogeneous MEMS and IC integration

Heterogeneous SoC integration joins MEMS and IC substrates through via-first or via-last processes. Via-first simplifies integration and packaging, while via-last improves placement and scaling but requires more processing.

Heterogeneous MEMS and IC integration joins substrates containing fully or partially fabricated MEMS and IC structures to produce a heterogeneous SoC.
Via formation during layer transfer: Via-first processes form mechanical and electrical vias during layer transfer, enabling pre-fabricated MEMS components to integrate with CMOS wafers during bonding.Such processes can combine monocrystalline silicon MEMS with standard CMOS wafers and perform integration and packaging in one bonding step.
Via formation during layer transfer: Via-first integration requires aligned substrate-to-substrate bonding, limiting post-bonding alignment accuracy and complicating reliable interconnections below 10 µm.
Via formation after layer transfer: Via-last processes form vias after layer transfer, avoiding the need for wafer-to-wafer alignment and defining component placement through lithography.They can provide sub-µm vias and membrane-to-IC spacing set by bonding-layer thickness, from below 100 nm to several tens of µm.
Via formation after layer transfer: Via-last integration supports dense IC-integrated MEMS using high-performance materials, but it requires more processing steps than typical via-first processes.

4 OUTLOOK AND CONCLUSIONS

MEMS–IC integration spans flexible multi-chip and dense SoC approaches, with trade-offs involving complexity, yield, packaging, footprint, and electrical performance. Emerging 3D and heterogeneous techniques increasingly combine high integration density with manufacturing and cost advantages.

Multi-chip solutions are flexible, less complex, faster to develop, and cost-effective across MEMS and IC chip sizes, but have lower density, larger footprints, weaker EMC robustness, and higher parasitics than SoC solutions.
SoC solutions provide high integration density and small dimensions, which are necessary for some large transducer arrays, but require greater complexity, reduced flexibility, and longer development times.
Low fabrication yield in either process can reduce aggregate SoC yield, while multi-chip assembly can pair known-good dies; mismatched chip sizes can also make SoC wafer area economically impractical.
SoC wafer-level packaging and consolidated testing can offset lower yield through reduced chip-level packaging, wire bonding, and testing costs.
3D stacking with smaller through-substrate vias enables thin, compact hybrid systems with lower interconnect parasitics while retaining multi-chip advantages.
Heterogeneous SoC integration places high-performance MEMS materials on standard CMOS wafers, allowing suitable CMOS selection and shared MEMS–CMOS chip area.
Heterogeneous approaches have gained market share by supporting fabless and fab-light models, using foundry CMOS sources, shrinking devices, and enabling multiple sensors on one chip.
Future multi-chip and SoC developments converge toward higher integration density, smaller and cheaper components, combined sensing functions, and specialized signal processing.