Source-linked AI summary
A 0.3-2.6 TOPS/W Precision-Scalable Processor for Real-Time Large-Scale ConvNets
Bert Moons, Marian Verhelst
TL;DR
CNNs deliver near-human performance but are typically energy-intensive, motivating hardware that adapts computation to varying precision and sparsity. This work implements a programmable processor combining precision and voltage scaling with guarded sparse computation, achieving up to 3.9x higher energy efficiency than non-scalable state-of-the-art systems.
Problem
CNNs offer near-human performance but are typically expensive in energy, while existing embedded solutions keep computational precision constant instead of adapting to varying requirements.
Method
The processor combines a precision-scalable 2D-SIMD MAC array, dynamic precision and voltage scaling, and guarded memory fetches and operations for sparse CNN computation.
Results
Up to 3.9x energy-efficiency improvement over non-scalable state-of-the-art systems is achieved, with up to 2.6 real TOPS/W in 4-bit mode.
Takeaways & Limitations
The processor supports programmable, throughput-preserving low-power CNN execution across AlexNet, LeNet-5, and a general 16-bit CNN.
Abstract
from arXiv · showhide
A low-power precision-scalable processor for ConvNets or convolutional neural networks (CNN) is implemented in a 40nm technology. Its 256 parallel processing units achieve a peak 102GOPS running at 204MHz. To minimize energy consumption while maintaining throughput, this works is the first to both exploit the sparsity of convolutions and to implement dynamic precision-scalability enabling supply- and energy scaling. The processor is fully C-programmable, consumes 25-288mW at 204 MHz and scales efficiency from 0.3-2.6 real TOPS/W. This system hereby outperforms the state-of-the-art up to 3.9x in energy efficiency.