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Millimeter Wave Receiver Efficiency: A Comprehensive Comparison of Beamforming Schemes with Low Resolution ADCs

Waqas bin Abbas, Felipe Gomez-Cuba, Michele Zorzi

arXiv:1607.03725v6cs.ITmath.IT

TL;DR

The paper examines how analog, hybrid, and digital combining compare in spectral and energy efficiency, questioning the conventional view that hybrid combining is preferable and digital combining consumes the most power. It analyzes the trade-off among these architectures and finds that which scheme fares better depends on the channel and hardware scenario, with a wide regime favoring low-bit digital combining.

  • Problem

    The paper questions the conventional view that hybrid combining is preferable and that digital combining consumes the most power.

    Source: §VI · p. 28

  • Method

    The paper studies the spectral- and energy-efficiency trade-off among analog, digital, and hybrid combining architectures.

    Source: §VI · p. 28

  • Results

    Analog combining is better in only one scenario and hybrid combining in only one, while digital combining outperforms hybrid combining in several aspects in other channel and hardware scenarios.

    Source: §VI · p. 28

  • Takeaways & Limitations

    A wide regime favors low-bit digital combining, challenging the claim that digital combining consumes the most power when that claim relies only on high-bit ADC power.

    Source: §VI · p. 28

Abstract

from arXiv · show

In this work, we study the achievable rate and the energy efficiency of Analog, Hybrid and Digital Combining (AC, HC and DC) for millimeter wave (mmW) receivers. We take into account the power consumption of all receiver components, not just Analog-to-Digital Converters (ADC), determine some practical limitations of beamforming in each architecture, and develop performance analysis charts that enable comparison of different receivers simultaneously in terms of two metrics, namely, Spectral Efficiency (SE) and Energy Efficiency (EE). We present a multi-objective utility optimization interpretation to find the best SE-EE weighted trade-off among AC, DC and HC schemes. We consider an Additive Quantization Noise Model (AQNM) to evaluate the achievable rates with low resolution ADCs. Our analysis shows that AC is only advantageous if the channel rank is strictly one, the link has very low SNR, or there is a very stringent low power constraint at the receiver. Otherwise, we show that the usual claim that DC requires the highest power is not universally valid. Rather, either DC or HC alternatively result in the better SE vs EE trade-off depending strongly on the considered power consumption characteristic values for each component of the mmW receiver.

I. INTRODUCTION

This section compares analog, hybrid, and digital combining in spectral and energy efficiency while accounting for total receiver power and ADC characteristics. It examines how ADC assumptions shape the relative advantages of these architectures.

I. INTRODUCTION

  • In most use cases, DC is more attractive than HC in both SE and EE, and low-resolution DC can consume less power when all receiver components are counted.The paper argues that judging DC power from ADC consumption alone gives an incomplete comparison.Source: §I · p. 3
  • As SNR rises, more ADC bits are needed to approach unquantized-system SE, while EE has an optimal bit resolution related to SNR and inversely to ADC power figure of merit.The paper states that an EE-maximizing bit count exists for all combining schemes.Source: §I · p. 3
  • AC is the best option in both EE and SE only for a single-path channel, very low SNR, or a very stringent receiver power constraint.The introduction presents these as special regimes rather than general conditions.Source: §I · p. 3
  • HC is preferable to DC only when few paths, a very low RF-chain-to-antenna ratio, channel-matched RF-chain count, and a pessimistic high-power ADC model coincide.The paper describes this as a conjunction of favorable system properties for HC.Source: §I · p. 3
  • Because future mmW system characteristics are unsettled, the authors characterize DC as the most future-proof architecture, with AC and HC favored only in exceptional scenarios.The introduction says those special conditions are the exception rather than the rule.Source: §I · p. 3

A. Related Work

  • The authors identify their work as the first comparison of AC, DC, and HC with finite-resolution ADCs across both EE and SE trade-offs.They also state that their model identifies and overcomes limitations in earlier frameworks.Source: A. Related Work · pp. 4–5
  • Some prior HC studies benchmark against ideal unquantized DC, assessing rate proximity rather than which architecture uses less power, and assume HC has better EE than quantized DC.The paper notes that this assumption is unverified when DC uses a carefully chosen low bit count.Source: A. Related Work · p. 5
  • Earlier analyses may focus only on ADC power or omit signal splitters, whereas this work accounts for the power consumption of all receiver components.The paper notes that splitters are needed to route antenna signals to multiple phase-shifter arrays and have non-negligible power consumption.Source: A. Related Work · p. 5
  • ADC power-consumption figures of merit vary by four orders of magnitude, and the paper classifies them as legacy, existing state-of-the-art, or projected future values.Source: A. Related Work · p. 5
  • HC outperforms DC only with legacy ADCs, so literature using pessimistic ADC figures of merit tends to overestimate HC’s benefits.Source: A. Related Work · p. 5
  • The authors publish a simulation viewing tool that lets readers modify component power values and reproduce prior results by setting omitted components to zero.Source: A. Related Work · p. 5

II. SYSTEM MODEL

The system model treats communication as a point-to-point MIMO link over a clustered multipath mmW channel. The analysis expresses spectral and energy efficiency in terms of antenna count and link SNR, and examines channels with different ranks.

II. SYSTEM MODEL

  • SE and EE expressions are derived as functions of antenna count and link SNR, with results applicable to mmW networks having those values.Finite-resolution bits are considered at the receiver only.Source: §II · p. 6
  • The link is modeled as a fast block-fading MIMO channel, and capacity is the ergodic capacity averaged over realizations of H.The transmit and receive arrays are uniform linear arrays with half-wavelength antenna spacing.Source: §II · p. 6
  • The channel is modeled with a small number of propagation paths grouped into clusters, with path angles varying around each cluster’s mean direction.The model uses distance-dependent path loss and small-scale fading for individual paths.Source: §II · pp. 6–7
  • Three channel-rank settings are examined: rank 1, low rank with typically 4–5 dominant eigenvalues, and a higher-rank case with typically 8–10.They are formed using Nc = Np = 1, Nc = 1 and Np = 10, and Nc = 2 and Np = 10, respectively.Source: §II · p. 7

A. Quantized Received signal

The section introduces AQNM as an approximation for evaluating quantized received signals and then applies it to the receiver signal model. Quantization noise depends on ADC resolution, and quantized SNR behaves differently at low and high SNR.

A. Quantized Received signal

  • AQNM models quantization as additive Gaussian noise whose power is inversely proportional to quantizer resolution, with a 2^-b factor relative to receiver input power.The exact nonlinear one-bit model is difficult to extend to higher bit counts.Source: A. Quantized Received signal · p. 7

B. Received Signal Model with AQNM

  • In the received-signal model, the signal may undergo analog processing before ADC conversion, with additive quantization noise and η inversely proportional to the square of ADC resolution.η ∝ 2^-2b.Source: B. Received Signal Model with AQNM · p. 8
  • At low SNR, quantized SNR is approximately (1 − η)γ; at high SNR with finite ADC bits, η approaches zero and quantized SNR approaches unquantized SNR γ.Source: B. Received Signal Model with AQNM · p. 9

III. RECEIVER ARCHITECTURES AND ACHIEVABLE RATES

The paper compares analog, digital, and hybrid receiver processing under quantization, assuming ideal fully digital transmitter processing and CSI at both ends. Analog combining reduces the received signal to one dimension before quantization, but its phase-only, constant-amplitude constraint limits beamforming.

III. RECEIVER ARCHITECTURES AND ACHIEVABLE RATES

  • The analysis compares Analog, Digital, and Hybrid receiver architectures, with ideal fully digital transmitter processing and CSI available at both transmitter and receiver.The architectures differ in analog processing before the ADC, which changes the number of RF and ADC units and the digital signal dimensions.Source: §III · p. 10

A. Analog Combining

  • Analog combining places multiple-antenna processing in the analog domain to reduce power consumption, delivering a scalar signal to one RF and ADC chain.The receiver uses one phase shifter per antenna and an analog signal adder.Source: A. Analog Combining · p. 10
  • Because analog combining permits only phase changes to constant-amplitude coefficients, its optimal beamformer is constrained rather than the unconstrained maximum-gain vector.The model uses an approximate solution that projects the unconstrained optimum onto the constant-amplitude vector space.Source: A. Analog Combining · p. 11

B. Digital Combining

Digital combining performs multiple-antenna processing after quantization, with one RF and ADC chain per receive antenna. It uses channel singular vectors and water filling, enabling both beamforming and spatial multiplexing without constant-amplitude constraints on the receive combiner.

B. Digital Combining

  • Digital combining performs all multiple-antenna processing digitally, sending each antenna’s signal to a dedicated RF and ADC chain before digital MIMO processing.The digital processor can spatially multiplex up to min(Nt, Nr) streams.Source: B. Digital Combining · p. 12
  • The design uses the channel’s singular vectors for transmit beamforming and receive combining, then allocates transmit power across singular values with water filling.The paper uses water filling as a lower-bound rate approximation because the quantization-noise dependence on Q means it may not maximize the rate expression.Source: B. Digital Combining · p. 12
  • At low SNR, water filling assigns all power to the maximum singular value, while the optimal number of streams may be below min(Nt, Nr).Digital combining provides spatial multiplexing gains at high SNR and beamforming power gains at low SNR.Source: B. Digital Combining · pp. 12–13
  • Digital combining’s capacity is always greater than analog combining’s because it imposes no constant-amplitude constraint on the receive combiner.At low SNR, its capacity is similar to analog combining’s.Source: B. Digital Combining · p. 13

C. Hybrid Combining

Hybrid combining uses analog processing to reduce the received signal to fewer dimensions than digital combining, then applies digital MIMO processing. Its RF combiner remains subject to constant-amplitude constraints, limiting capacity relative to digital combining.

C. Hybrid Combining

  • Hybrid combining balances digital combining’s capacity and analog combining’s low power consumption by using both analog and digital multiple-antenna processing.Its analog stage reduces the received signal to NRF dimensions, where 1 < NRF < Nr, before quantization and digital MIMO processing.Source: C. Hybrid Combining · p. 13

S(WRF H)

  • Hybrid combining designs its baseband combiner and transmitter beamformer from the equivalent channel’s singular vectors, while the RF combiner is constrained by phase shifters.The RF combiner is selected through projection of the equivalent-channel eigenvectors onto the space of constant-amplitude matrices.Source: C. Hybrid Combining · pp. 13–14, S(WRF H) · p. 14
  • Hybrid capacity is upper bounded by digital-combining capacity because its RF combiner must satisfy the analog constant-amplitude constraint.The hybrid receive matrix has dimension NRF rather than Nr because of its limited number of RF chains.Source: S(WRF H) · p. 14

D. Capacity Results

Across the reported propagation cases, digital combining outperforms analog and hybrid combining in capacity, while analog combining is most competitive for rank-one channels at high ADC resolution. The energy-efficiency analysis accounts for receiver components beyond ADCs and compares receiver architectures using total power consumption.

D. Capacity Results

  • Across the tested architectures, capacity saturates beyond a threshold number of ADC bits, and that threshold rises with the unquantized-signal SNR.The figures compare capacity against ADC bits for Np = 1 and Np = 10.Source: D. Capacity Results · p. 15, Figure 5 · p. 15
  • Digital combining outperforms analog and hybrid schemes for any number of propagation paths; analog combining is competitive with them for Np = 1 only at high ADC-bit counts.For Np = 10, analog combining achieves significantly lower rates because it cannot exploit spatial multiplexing.Source: D. Capacity Results · pp. 15–16
  • Hybrid combining’s rate remains slightly below digital combining’s because of its RF constant-amplitude constraint and digital combining’s ability to multiplex up to min(Nt, Nr) streams.The paper identifies analog combining’s strongest appeal as single-path or sparse propagation environments.Source: D. Capacity Results · p. 16

IV. ENERGY EFFICIENCY ANALYSIS

  • Evaluating energy efficiency requires considering analog-block power as well as ADC power, since hybrid combining may require many analog blocks and ADCs simultaneously.The paper notes that phase shifters and analog combiners can substantially penalize hybrid combining when their power consumption is non-negligible.Source: §IV · p. 16

A. Power Consumption Model

ADC POWER PER SAMPLE AND PER LEVEL

  • The ADC power scenarios distinguish an ideal future low-power ADC, a state-of-the-art ADC, and a legacy ADC.The listed values are 5 fJ/step/Hz, 494 fJ/step/Hz, and 12.5 pJ/step/Hz, respectively.Source: ADC POWER PER SAMPLE AND PER LEVEL · p. 17

+ NRF(PRF + PC + 2PADC)

The analysis models receiver-component power, including ADC costs, and examines how ADC technology and SNR shape energy efficiency. The results show that the best architecture and ADC-bit count depend on those power and channel conditions.

+ NRF(PRF + PC + 2PADC)

  • ADC power rises exponentially with bit count and linearly with bandwidth and Walden’s figure of merit; other component power is independent of bandwidth and bit count.The analysis considers three ADC technology generations.Source: + NRF(PRF + PC + 2PADC) · p. 17

B. EE Results

  • DC offers the highest EE with HPADC, while with PHPADC its EE is similar to HC and AC and peaks at very few bits.Beyond DC’s optimal bit count, its EE falls rapidly; at the same bit count, AC and HC can outperform it when the bit count is not very low.Source: Figure 6 · p. 18, Figure 7 · p. 18, B. EE Results · p. 19
  • All three schemes have an optimal ADC-bit count: EE rises before that point and falls after it as ADC power grows faster than capacity.The optimum reflects capacity saturation and the ADC power-consumption model.Source: B. EE Results · p. 18
  • PHPADC power rises faster with bit count than HPADC power, while capacity is unchanged across ADC models, so higher-power ADCs require fewer optimal bits.Source: B. EE Results · pp. 18–19
  • Higher SNR delays capacity saturation and increases the bit count that maximizes EE.Source: B. EE Results · p. 19
  • At low SNR, AC can outperform HC because water-filling concentrates power on the strongest singular value, limiting HC’s multiplexing advantage while its extra analog components add power.With similar capacity, HC’s greater component power can make its EE worse.Source: B. EE Results · p. 19

V. SIMULATION RESULTS

The simulations compare receiver architectures using SE–EE charts and examine how channel paths and operating conditions affect their trade-offs. AC’s advantage is confined to rank-one propagation, while the HC–DC comparison depends on the operating region rather than matching bit counts alone.

V. SIMULATION RESULTS

  • Charts plot each architecture’s SE versus EE as ADC bits b increase from 1 to 8 in increments of 1; highest points indicate highest capacity or SE, rightmost points highest EE, and top-right points are better.Source: §V · p. 19
  • AC has much better EE than HC and DC at similar SE when Np = 1, but that advantage disappears with spatial-multiplexing gain as Np increases.For Np = 1, the channel has only one singular value, so there is no spatial-multiplexing gain; AC’s performance degrades as Np increases.Source: Figure 8 · p. 20, Figure 9 · p. 20, A. AC is superior only if Nc = 1 · pp. 20–21

B. HC versus DC: A Baseline

  • At high SNR in the baseline comparison, HC reaches a larger EE at nearly the same SE as DC, but the HC advantage is fragile when system conditions change.The comparison considers complete operating regions, not just points with equal ADC-bit counts.Source: B. HC versus DC: A Baseline · pp. 21–22
  • AC always uses the least absolute power, but its lower SE makes it preferable when low power matters more than achieving a higher rate.Source: B. HC versus DC: A Baseline · p. 22
  • DC can still provide better EE than HC in particular operating regions, including at low SNR with few ADC bits.For the cited low-SNR comparison, 2-bit DC achieves approximately 10% more EE than 5-bit HC at the same reported rate.Source: B. HC versus DC: A Baseline · p. 22

C. Improvement of ADCs

The comparison examines how improved ADC power models change the SE–EE trade-off among AC, HC, and DC. As ADC power becomes less significant, DC gains ground and dominates HC in the reported LPADC case.

C. Improvement of ADCs

  • As ADC power decreases, EE improves for all schemes, and DC comes to dominate HC across SE and EE levels.The comparison includes HPADC and LPADC models.Source: C. Improvement of ADCs · pp. 22–23, Figure 10 · p. 23, Figure 11 · p. 23
  • The compared ADC figure of merit rises from 0–2 in the baseline to 0–5 in HDADC and 0–9 in LPADC; this improvement is exploited mostly by DC, which reaches the most top-right chart regions.Source: C. Improvement of ADCs · p. 23
  • With HPADC at 7 or 8 bits, DC has lower EE than HC in the same-bit comparison, but DC also reaches 4.5 Gb/J at 42 bps/Hz with 6 bits.The cited same-bit values are DC at 3.2 and 2 Gb/J with 43 bps/Hz, versus HC at 3.5 Gb/J with 35 bps/Hz.Source: C. Improvement of ADCs · p. 23
  • With LPADC, DC provides better EE and SE than the other schemes even at the same bit count, and increasing bits up to 8 raises both EE and SE.ADC power is sufficiently low in this model that the curves do not wrap.Source: C. Improvement of ADCs · p. 23

D. Reduced number of receive antennas

The simulations vary receive-antenna count and scattering to show how channel rank and power constraints change the SE–EE trade-off. DC’s advantage grows when channel rank exceeds HC’s RF-chain capacity, while lower antenna counts alter both efficiency and feasible operating regions.

D. Reduced number of receive antennas

  • Reducing Nr decreases SE and increases EE across all combining schemes, as array gain falls while power consumption declines with antenna count.The reported SE reduction is logarithmic, while power consumption falls linearly with Nr.Source: D. Reduced number of receive antennas · p. 24
  • With reduced Nr, DC contains HC’s operational region at low SNR; at high SNR their maximum EE difference narrows, with HC reaching 4 Gb/J at 16 bps/Hz versus DC’s 3.7 Gb/J at that SE.Source: D. Reduced number of receive antennas · pp. 24–25
  • Under the reduced-antenna power chart, AC is the only viable architecture below 2 W; HC outperforms DC from 4 to 10 W, while DC outperforms HC above 10 W.Between 2 and 4 W, a small region favors DC; AC is recommended if receivers cannot exceed 2 W.Source: D. Reduced number of receive antennas · p. 25

E. Increased scattering reflections

  • With Np = 10, Nc = 2, and NRF = 4, DC reaches 2.85 Gb/J at 35 bps/Hz with 2 bits, versus HC’s 2.7 Gb/J at that rate with 7 bits.DC also reaches 45 bps/Hz at 2.55 Gb/J with 3 bits.Source: E. Increased scattering reflections · p. 25, Figure 13 · p. 26
  • When channel rank exceeds HC’s four RF chains, HC cannot exploit all dominant eigenvalues, so its SE improvement is marginal; even a mild increase in scattering diversity makes DC superior to HC.An increase in channel rank raises SE without changing power consumption, increasing EE.Source: E. Increased scattering reflections · p. 26

F. Increased number of HC RF chains

The section examines how adding HC RF chains shifts the SE–EE trade-off: HC gains spectral efficiency but pays in energy efficiency, while DC generally remains competitive. The conclusion limits AC’s advantage to narrow conditions and shows that the DC–HC comparison depends on channel scattering and receiver-component power assumptions.

F. Increased number of HC RF chains

  • With NRF increased to 8, HC improves SE but loses EE; at high SNR it reaches 50 bps/Hz with EE under 2.5 Gb/J.Figure 14 compares SE and EE for the PHPADC model with Nr = 64, NRF = 8, Nc = 2, and Np = 10.Source: F. Increased number of HC RF chains · p. 27, Figure 14 · p. 27
  • Increasing HC RF chains trades improved SE for lower EE, because more RF chains increase analog phase-array power consumption.The comparison reports improved SE and decreased EE relative to Figure 13; the higher chain count enables spatial multiplexing across more independent paths.Source: F. Increased number of HC RF chains · p. 27
  • DC leads on both EE and SE in most of the comparison, although HC has a small high-SNR region near 50 bps/Hz and 2.5 Gb/J outside DC’s curve.At low SNR, DC always outperforms HC.Source: F. Increased number of HC RF chains · p. 27
  • As scattering grows, keeping HC’s RF-chain count limits SE, while increasing it penalizes EE; neither option preserves HC’s advantage over DC.The authors conclude that DC works better when scattering is not so poor; as Nc = NRF = Nr, HC becomes a wasteful implementation of DC.Source: F. Increased number of HC RF chains · pp. 27–28

VI. CONCLUSIONS

  • AC is advantageous only in a rank-1 channel or under very tight receiver power constraints; the conclusion also says DC’s power disadvantage is not universal.The authors link that DC claim to ADC power assumptions, noting that even slight ADC improvements make DC much superior.Source: §VI · p. 28
  • The conclusion says DC can outperform HC across non-sparse channels: with fewer HC RF chains it can offer higher rate, and with more chains similar rate but better EE.The authors describe their scattering-diversity calculations as conservative in favor of HC.Source: §VI · pp. 28–29
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