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Self-Directed Channel Memristor for High Temperature Operation

Kristy A. Campbell

arXiv:1608.05357v1cond-mat.mes-hall

TL;DR

Ion-conducting memristors are of interest for applications including non-volatile memory and neuromorphic computing. This paper describes a layered self-directed channel device that changes resistance through Ag movement in its active layer. The devices operate continuously at 150 °C and remain functional through at least 1 billion cycles at room temperature and 140 °C.

  • Problem

    Ion-conducting memristors are studied for potential use in non-volatile memory, neuromorphic and bio-inspired computing, and threshold logic.

    Source: §I · p. 1

  • Method

    The layered SDC device uses Sn ions to facilitate Ag incorporation into Ge2Se3 channels, where Ag movement changes resistance.

    Source: §II · pp. 2–3

  • Results

    SDC devices operate continuously at 150 °C and remain functional through at least 1 billion cycles at room temperature and 140 °C.

    Source: §V · p. 5

  • Takeaways & Limitations

    The SDC structure requires no photodoping or thermal annealing and uses one in-situ deposition step for all device layers.

    Source: §II · p. 2

    Data retention in intermediate resistance states is under study and depends on the programming conditions.

    Source: §V · p. 5

Abstract

from arXiv · show

Ion-conducting memristors comprised of the layered chalcogenide materials Ge2Se3/SnSe/Ag are described. The memristor, termed a self-directed channel (SDC) device, can be classified as a generic memristor and can tolerate continuous high temperature operation (at least 150 {\deg}C). Unlike other chalcogenide-based ion conducting device types, the SDC does not require complicated fabrication steps, such as photodoping or thermal annealing, making these devices faster and more reliable to fabricate. Device pulsed response shows fast state switching in the 10E-9 s range. Device cycling at both room temperature and 140 {\deg}C show cycling lifetimes of at least 1 billion.

I. INTRODUCTION

This work describes an ion-conducting memristor whose resistance changes through Ag+ movement in channels within its active layer. It presents electrical measurements of the device, including its temperature response, cycling lifetime, and pulsed response.

I. INTRODUCTION

  • The self-directed channel (SDC) device changes resistance through Ag+ movement in channels within its active layer.The amount of Ag in the channel determines device resistance.Source: §I · p. 1
  • The paper presents electrical properties measured through DC sweeps, sinusoidal inputs, cycling, and programming pulses.Source: §I · p. 1
  • Memristors are studied for potential use in non-volatile memory, neuromorphic and bio-inspired computing, and threshold logic.Source: §I · p. 1

II. DEVICE OPERATION

The SDC device forms Ag-containing channels within a Ge2Se3 active layer, using the layered structure to support ion movement and resistance tuning. Its fabrication avoids photodoping and thermal annealing, and the device is described as capable of continuous operation at 150 °C.

II. DEVICE OPERATION

  • Unlike the SDC, CBRAM devices form and dissolve a metallic filament and typically require tightly controlled metal incorporation by deposition, photodoping, or annealing.The cited fabrication methods can lower maximum temperature exposure because of glass crystallization and metal diffusion concerns.Source: §II · pp. 1–2
  • The Ge2Se3/Ag/Ge2Se3 Ag-source layer is separated from the active layer, supporting operation at least 150 °C and processing above 250 °C.The active layer maintains a glass transition temperature of about 350 °C.Source: §II · p. 2
  • All layers, including the top electrode, are deposited in one in-situ sputtering step without photodoping or annealing.The active layer has a stated acceptable thickness range of 300–500 Å, and wafer yields are reported above 90%.Source: §II · p. 2
  • The first operation drives Sn ions from SnSe into Ge2Se3, facilitating Ag incorporation at Ge-Ge bonding sites and channel formation.The channel follows the initial Ge-Ge dimers in the glass.Source: §II · pp. 2–3
  • Ag agglomeration sites in the self-directed channel create a pathway whose resistance changes as Ag moves onto or away from those sites.The channel need not be a metallic filament spanning the electrodes; Ag concentration and site spacing determine resistance.Source: §II · p. 3

A. Device Structure and Fabrication

Devices use a via structure with top and bottom electrodes and are fabricated on 100 mm p-type silicon wafers. The active switching layer is a 300 Å Ge2Se3 layer adjacent to the bottom electrode.

B. Device Structure and Fabrication

B. Electrical Measurements

Electrical measurements covered DC behavior, sinusoidal response, cycling, and programming pulses. The sinusoidal frequency sweep was used for memristor classification, while separate pulsed measurements examined programming response.

B. Electrical Measurements

  • DC measurements varied compliance current and temperature, using wafer-level testing at 23, 50, 100, and 150 °C after at least 30 minutes of equilibration.The DC sweeps used a Write/Erase/Write sequence, with Write from 0 to 1 V and Erase from 0 to –1 V.Source: B. Electrical Measurements · p. 3
  • Sinusoidal classification measurements applied 10 cycles per frequency from 0.5 Hz to 100 kHz; this frequency response was not a measure of device speed.The WGFMUs measured current directly without external circuits or current-limiting series resistors.Source: B. Electrical Measurements · p. 3
  • Cycling used a 1 kHz arbitrary waveform and a 10 kΩ load resistor to limit device current.An oscilloscope in persistence mode recorded the response every decade of cycling.Source: B. Electrical Measurements · p. 3

A. Quasi-Static DC Measurements

The SDC switches between low- and high-resistance states through write and erase sweeps, and its forming sweep uses the same potential as normal operation. The programmed low-resistance state depends on write-sweep compliance current, while heating to 150 °C for two days did not change the subsequent DC IV response.

A. Quasi-Static DC Measurements

  • Write sweeps form a conductive channel and set low resistance; erase sweeps move Ag out of the channel and restore high resistance.The first post-fabrication write sweep does not require a higher potential than normal operation, at temperatures up to at least 150 °C.Source: A. Quasi-Static DC Measurements · p. 3
  • After a 1 mA compliance-current write, erased resistance typically stays at or below 200 kΩ, with a permanent impact.The programmed low-resistance state also depends significantly on write-sweep compliance current.Source: A. Quasi-Static DC Measurements · p. 4
  • Two days at 150 °C produced no difference in subsequent DC IV response versus devices that had not been heated.Fig. 3 plots resistance against compliance current and operating temperature, distinguishing written states with dashed lines and erased states with solid lines.Source: A. Quasi-Static DC Measurements · p. 4, Figure 3 · p. 4

B. Device Response to Sinusoidal Input

Across sinusoidal inputs from 0.5 Hz to 100 kHz, the device’s IV curves pass through the origin and their lobe area shrinks with increasing frequency, eventually collapsing into a line. This response is used to classify the device as a generic memristor, not to characterize programming-pulse response.

B. Device Response to Sinusoidal Input

C. Lifetime Cycling

The devices cycled at both room temperature and 140 °C reached at least one billion cycles. Read pulses during the 140 °C test verified that the device was programmed as expected.

C. Lifetime Cycling

  • At both room temperature and 140 °C, devices cycled for at least one billion cycles.The 140 °C waveform included low-amplitude read pulses after write and erase peaks; readback showed the expected programmed state.Source: C. Lifetime Cycling · p. 4, Figure 5 · p. 4
  • At 140 °C, read pulses after write and erase peaks verified that the device reached its expected programmed state.Source: C. Lifetime Cycling · p. 4
  • During erase, the device conducts until an erase-threshold voltage, after which resistance increases and voltage across the load decreases.Source: C. Lifetime Cycling · p. 4

D. Pulsed Response

The pulsed response supports both binary erase/write switching and incremental resistance programming.

D. Pulsed Response

  • 70 ns erase/write pulses demonstrate binary switching between a low-resistance state and a high-resistance state.The pulse widths are reported as 70 ns FWHM.Source: D. Pulsed Response · p. 4, Figure 6 · p. 5
  • Erase pulses drive resistance above 1 MΩ, and a subsequent write pulse returns it to approximately 1 kΩ.Repeated erase/write sequences cycle the device between high and low resistance states.Source: D. Pulsed Response · p. 5, Figure 6 · p. 5
  • Reduced pulse amplitudes and widths of 70–500 ns FWHM enable continuous resistance programming, with erase pulses raising resistance from 12 kΩ to approximately 60 kΩ and write pulses lowering it to 9 kΩ.The sequence uses eight erase pulses followed by eight write pulses.Source: D. Pulsed Response · p. 5

V. CONCLUSIONS

The conclusions describe SDC devices that operate continuously at high temperature without photodoping or thermal annealing. Their programmed resistance varies little with temperature, and devices cycle for at least one billion cycles at room temperature and 140 °C.

V. CONCLUSIONS

  • Continuous operation at 150 °C and fabrication without photodoping or thermal annealing distinguish the SDC devices.All device layers, including the top electrode, are deposited in one in-situ step using a standard sputter tool.Source: §V · p. 5
  • At room temperature and 140 °C, devices remain functional through at least 1 billion cycles; programmed resistance shows no significant variation with temperature up to 150 °C.Source: §V · p. 5
  • A sinusoidal response from 0.5 Hz to 100 kHz classifies the devices as generic memristors, and DC compliance limiting or pulsed operation programs continuous resistance states.Intermediate-state retention remains under study and depends on programming conditions.Source: §V · p. 5
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