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A near-threshold RISC-V core with DSP extensions for scalable IoT Endpoint Devices

Michael Gautschi, Pasquale Davide Schiavone, Andreas Traber, Igor Loi, Antonio Pullini, Davide Rossi, Eric Flamand, Frank K. Gurkaynak, Luca Benini

arXiv:1608.08376v1cs.AR

TL;DR

IoT endpoints require flexible processing from lightweight control to complex sensor workloads within milliwatt-level power budgets. The paper presents an open-source RISC-V core with DSP extensions, near-threshold optimization, and shared-memory-aware microarchitecture. The resulting system reports substantial speed, bandwidth, energy-efficiency, and voltage-scalability gains across sensor-processing workloads.

  • Problem

    IoT endpoints need flexible computation across a wide workload range under extremely tight power budgets, while single-core MCUs are inadequate for complex parallel sensor processing.

  • Method

    The paper designs an open-source RISC-V core for near-threshold tightly coupled multi-core clusters using DSP/SIMD extensions, L0 storage, and shared-memory-aware microarchitectural optimizations.

  • Results

    3.5× faster and 3.2× more energy-efficient signal-processing kernels are reported on average, with 8.3× lower shared-memory bandwidth and scalable multi-core and near-threshold operation.

  • Takeaways & Limitations

    The extended programmable architecture combines general-purpose flexibility with substantially improved efficiency for data-intensive sensor processing in scalable IoT clusters.

Abstract

from arXiv · show

Endpoint devices for Internet-of-Things not only need to work under extremely tight power envelope of a few milliwatts, but also need to be flexible in their computing capabilities, from a few kOPS to GOPS. Near-threshold(NT) operation can achieve higher energy efficiency, and the performance scalability can be gained through parallelism. In this paper we describe the design of an open-source RISC-V processor core specifically designed for NT operation in tightly coupled multi-core clusters. We introduce instruction-extensions and microarchitectural optimizations to increase the computational density and to minimize the pressure towards the shared memory hierarchy. For typical data-intensive sensor processing workloads the proposed core is on average 3.5x faster and 3.2x more energy-efficient, thanks to a smart L0 buffer to reduce cache access contentions and support for compressed instructions. SIMD extensions, such as dot-products, and a built-in L0 storage further reduce the shared memory accesses by 8x reducing contentions by 3.2x. With four NT-optimized cores, the cluster is operational from 0.6V to 1.2V achieving a peak efficiency of 67MOPS/mW in a low-cost 65nm bulk CMOS technology. In a low power 28nm FDSOI process a peak efficiency of 193MOPS/mW(40MHz, 1mW) can be achieved.

I. INTRODUCTION

The paper targets flexible, scalable IoT processing under milliwatt-level power constraints by combining near-threshold parallelism with an open RISC-V core optimized for shared-memory operation.

  • Motivation: IoT endpoints need ultra-low-power processing while supporting increasingly complex, parallel sensor workloads.Single-core MCUs are efficient for control and lightweight processing but are insufficient for more complex algorithms on parallel sensor streams.
  • Motivation: Near-threshold operation improves energy efficiency, while parallel computing compensates for its frequency loss.The authors propose flexible and scalable programmable cores as an alternative to task-specific hardware accelerators.
  • Design challenge: Shared memory hierarchy design is a major challenge because multi-core parallelism increases access latency, energy, and contention.TCDM and standard-cell memories support shared access and near-threshold operation, but memory access remains critical.
  • Approach: The proposed architecture uses an open-source RISC-V ISA to enable application-specific extensions for near-threshold parallel clusters.The work specifically targets ISA and microarchitecture optimization for tightly coupled shared-memory operation.
  • Contributions: The design combines DSP arithmetic, SIMD dot-product and shuffle instructions, misaligned loads, an instruction L0 buffer, and an optimized pipeline.These mechanisms target computational density, load-store traffic, instruction-memory bandwidth, and near-threshold shared-memory timing.
  • Reported results: 3.5× faster and 3.2× higher energy efficiency are reported for signal-processing kernels using the extended instructions and microarchitectural enhancements.Convolution optimization with dot-product and shuffle instructions reduces shared-memory accesses and enables 3.9× speedup on four cores.

II. RELATED WORK

Prior IoT platforms trade flexibility, scalability, and energy efficiency across MCUs, DSPs, accelerators, and multi-core systems; this work focuses on shared-memory and memory-access bottlenecks in a scalable PULP cluster.

  • MCUs: Conventional IoT endpoints mainly use single-core MCUs for control and lightweight processing, limiting complex parallel sensor computation.Commercial examples commonly use above-threshold ARM Cortex-M processors.
  • DSPs and accelerators: DSPs, VLIW processors, and dedicated accelerators improve data-processing efficiency but trade away flexibility or general-purpose programmability.Dedicated accelerators can provide task-specific energy efficiency, while DSPs are harder to program than processors.
  • SIMD extensions: SIMD support is increasingly used for sensor data because typical ADC samples are 16 bits or less and multiple elements can be processed per instruction.ARM Cortex-M4 supports DSP functions and 16-bit dot products, while the cited discussion notes that an 8-bit equivalent is not supported.
  • Multi-core platforms: Existing heterogeneous dual-core MCUs are not scalable in memory hierarchy or core count because cores reside in separate subsystems with incompatible executable support.Academic multi-core platforms address some of these limitations with SIMD capabilities and reconfigurable vector machines.
  • PULP platform: The PULP platform uses configurable cores, shared instruction cache, and shared scratchpad memory to support parallel execution while controlling power.Its data memories combine per-core SRAM with voltage-scalable standard-cell memories, and clock gating permits operation down to a single-core controller.
  • Memory bottleneck: Memory access is a central bottleneck: a straightforward 5×5 convolution spends 389k of 625k single-core cycles on loads and stores, while parallelism can raise shared-memory contention by up to 20%.The paper therefore targets reduced data-memory traffic and contention through vector operations, L0 storage, and shared-memory-aware design.

IV. RISC-V CORE MICRO-ARCHITECTURE

The core microarchitecture is organized around extensions and optimizations that improve efficiency in multi-core shared-memory operation.

  • Architecture overview: The core design section details RISC-V ISA extensions and microarchitectural optimizations for efficient shared-memory multi-core execution.The pipeline is described before the individual components, including instruction-fetch, hardware-loop, and post-increment features.

A. Pipeline Architecture

The core uses a four-stage pipeline designed to balance throughput, hazards, and shared-memory timing in a near-threshold multi-core cluster. Its fetch path handles compressed and unaligned instructions through a pre-fetch buffer.

  • A. Pipeline Architecture: Higher pipeline depth can raise frequency but increases hazards and may reduce IPC, while added prediction and speculation increase power.
  • A. Pipeline Architecture: The shared TCDM uses multiple banks and a logarithmic interconnect, whose arbitration and interconnect add delay to data requests.
  • A. Pipeline Architecture: The four-stage organization balances request and return paths from shared TCDM banks, with useful clock skew applied to the longer memory return path.
  • A. Pipeline Architecture: A pre-fetch buffer fetches complete 128b cache lines, reducing shared instruction-cache contention while retaining 4 to 8 instructions locally.
  • A. Pipeline Architecture: The pre-fetch buffer combines split instruction halves, allowing unaligned instruction-cache accesses without stalls except around branches, hardware loops, or jumps.

C. Hardware-loops

Hardware loops reduce instruction-fetch and control-flow overhead for repeated code, while the pre-fetch buffer can also serve as a small loop cache. The design uses two loop-register sets as a cost-performance trade-off.

  • C. Hardware-loops: Hardware loops re-execute a loop by comparing the program counter with an end address and redirecting fetch to the start address until the counter reaches zero.
  • C. Hardware-loops: Hardware-loop control eliminates loop-counter tests and branches, reducing the number of instructions fetched from the instruction cache.
  • C. Hardware-loops: A loop buffer can remove fetch delay and reduce fetch power, amplifying the impact of hardware loops.
  • C. Hardware-loops: The implementation adds a controller and register sets storing loop counters, start addresses, and end addresses in CSR space.
  • C. Hardware-loops: Two loop-register sets provide the best measured trade-off, while each additional set costs approximately 1.5kGE.

D. Load-store unit

The load-store unit adds addressing and unaligned-access support to reduce instruction and register-file overhead in data-intensive SIMD workloads. Post-increment addressing is particularly effective for regular access patterns.

  • D. Load-store unit: Post-increment loads and stores automatically update address pointers, supporting register or immediate offsets beyond the basic immediate-offset addressing mode.
  • D. Load-store unit: Hardware LSU support handles unaligned accesses in one instruction and two cycles instead of five instructions and cycles in software.
  • D. Load-store unit: Up to 20% speedup is achieved with post-increment instructions for regular memory-access patterns such as matrix multiplication.
  • D. Load-store unit: Separate ALU and LSU register-file write ports allow post-increment loads to write back both loaded data and the updated address without contention.
  • D. Load-store unit: The vectorized datapath processes up to four 8b or two 16b elements in parallel, while shuffle operations prepare combinations of sub-words from two operands.

2) Fixed-Point support:

The fixed-point extensions support compact arithmetic across Q-formats and add operations for normalization, rounding, clipping, and bit manipulation. These instructions reduce code and execution overhead for sensor-processing workloads.

  • 2) Fixed-Point support:: Fixed-point arithmetic reuses the integer datapath and adds saturation, normalization, and rounding support for applications that do not require floating-point accuracy.
  • 2) Fixed-Point support:: The extensions support fixed-point operations in any Q-format subject to n + m < 32.
  • 2) Fixed-Point support:: The combined add-round-normalize instruction reduces the example from five to three instructions and saves two execution cycles for four Q1.11 values.
  • 2) Fixed-Point support:: The clip instruction saturates values outside bounds using existing comparator and adder hardware rather than significant additional ALU hardware.
  • 2) Fixed-Point support:: Bit-manipulation instructions support extraction, insertion, bit clear/set, population counting, and finding the first or last set bit.

4) Iterative Divider:

The core combines scalar, fixed-point, vector, and dot-product multiplication support, with hardware structures that improve throughput while controlling area and switching activity.

  • The multiplier integrates 32b×32b, fractional, and two dot-product multiplier modules.
  • One-cycle dot products multiply two vectors and accumulate up to four products and three additions into a 32b result.
  • Fixed-point instructions support multiply, accumulate, shifting, rounding, and normalization for 16b operands and 32b results.
  • The p.mulsRN instruction performs multiply, add, and shift in one cycle, reducing code size and cycle count.
  • 50% lower core power is achieved by clock-gating separate execution units through additional operand registers.

V. TOOLCHAIN SUPPORT

The toolchain extends GCC and binutils to expose the processor’s fixed-point, loop, pointer, vector, and SIMD capabilities, while dot products rely on built-ins.

  • GCC and binutils were modified to support the extended ISA, relocation schemes, fixed-point operations, hardware loops, and post-increment addressing.
  • Compiler pointer analysis is limited to a single loop level, missing opportunities across nested loop levels.
  • Compiler support automatically exposes sums of products and differences, favoring shorter multiply-accumulate forms to reduce energy.
  • Vector types and unaligned accesses enable SIMD-oriented vectorization for 4-byte or 2-short data.
  • Dot-product instructions are exposed through GCC built-ins because GCC does not automatically detect and map them as native internal operations.

VI. EXPERIMENTAL RESULTS

Hardware evaluations compare basic and extended RISC-V clusters, showing modest area overhead, low operating power, and instruction-level energy trade-offs.

  • The evaluation uses 72kB TCDM, 4kB instruction cache, synthesized 65nm CMOS clusters, and C benchmarks spanning common sensor-processing kernels.
  • The extended core adds 6.6kGE through additional execution units while retaining comparable size to the reference architectures.
  • The cluster occupies 1.30MGE, with dot-product and ALU extensions contributing 2% of area.
  • At 50MHz and 1.08V, total cluster power is 4mW, with the active core consuming 35%.
  • Arithmetic operations in the extended core show a 4% power increase because the extended core is larger.
  • A 50pJ shuffle operation replaces 3–4 simple ALU operations consuming 90–120pJ.

C. Function Kernel Performance

Benchmark results show that hardware loops and pointer extensions provide broad gains, while vector and dot-product support delivers the largest improvements for regular data-intensive kernels.

  • C. Function Kernel Performance: The benchmark suite covers cryptographic, control-intensive, transformation, linear-algebra, filtering, convolution, and motion-detection workloads.
  • C. Function Kernel Performance: 37% average speedup is achieved with hardware loops and post-increment extensions versus a plain RISC-V ISA.
  • C. Function Kernel Performance: 3.5× average speedup and up to 13.2× speedup are achieved on data-intensive kernels using vector types and the C built-in dot-product instruction.
  • C. Function Kernel Performance: 3.2× average energy gain is reported for the extended core across the evaluated applications.
  • C. Function Kernel Performance: 10.2× performance gain is reached for matrix multiplication when dot-product, hardware-loop, and post-increment extensions are jointly beneficial.
  • C. Function Kernel Performance: 28.9–46.1% of executed instructions are compressed, although the extended core has a lower ratio because vector instructions and built-ins lack compressed forms.

D. Convolution Performance

The extended RISC-V architecture substantially accelerates convolution processing through vector and instruction-set extensions while reducing memory traffic and energy. Four-core execution scales nearly ideally, although programmable cores remain slower and less energy-efficient than specialized accelerators.

  • Convolution evaluation: 2.2-6.9× overall speedup is achieved for convolutions with dot-product and shuffle instructions.The extensions alone provide up to 41% speedup, while dot-product and shuffle instructions add 1.7-6.4× gains.
  • Memory effects: 8.3× fewer load/store operations reduce shared-memory contentions from 17.8% to 6.2%.Vector operations reduce contentions from 11’100 to 390 by retaining coefficients in the register file and reorganizing pixels with move and shuffle instructions.
  • Energy evaluation: 2.2-7.8× higher energy efficiency is obtained for the 64×64 convolution image.The overall system power decreases in all evaluated cases except Conv 3x3 short, where it marginally increases by 5.3%.
  • Multi-core scaling: 3.9× speedup is achieved with four cores, while power increases by only 2.4× versus one core.The resulting energy savings are 1.6×, with negligible overhead at strip boundaries.
  • Accelerator comparison: The DSP-extended core is 11-26× slower than the HWCE accelerator, compared with 112× for the unextended core.The comparison shows that the extensions narrow the performance gap between programmable cores and specialized hardware.
  • Accelerator comparison: 15-25× more energy is consumed by the RISC-V core than by the Origami accelerator in the same technology.This comparison concerns energy rather than convolution execution speed.

E. Near-threshold operation

The paper evaluates ISA and microarchitectural extensions for scalable near-threshold RISC-V clusters. The extensions improve execution efficiency and memory behavior, while multi-core operation and advanced technology extend energy-efficient performance across operating points.

  • Near-threshold operation: 10× speedup is obtained from the proposed ISA extensions relative to a RISC-V or OpenRISC core without extensions.Hardware loops and post-increment instructions improve execution speed by 1.8× in Mia before dot-product instructions provide the largest additional gain.
  • Architecture: The core combines fixed-point, vector, hardware-loop, and post-incrementing instructions with a smart L0 fetch buffer.Dot-product and sum-of-dot-products instructions process up to four 8b or 16b multiplications and accumulations in one cycle.
  • Microarchitectural effects: 8.3× lower shared-memory bandwidth and up to 7.8× energy gains result from combining vector instructions with L0 storage.Load/store instructions require the most energy, making bandwidth reduction especially consequential for energy consumption.
  • Multi-core scaling: A four-core implementation delivers 3.9× the performance of a single core while consuming 2.4× more power.The extensions also reduce shared-memory contentions in multi-core implementations.
  • Near-threshold operation: 5× energy-efficiency gain is observed at 0.46V in the 28nm implementation, reaching 0.2GOPS at 1mW.The 28nm cluster is estimated to provide another 1.9× energy advantage over the reported 65nm implementation.
  • Scalability: 0.46-1.1V operation spans 1-68mW and 0.2-2.5GOPS, demonstrating scalable cluster operation.The reported 28nm cluster maintains the same throughput conditions across the stated voltage range.
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