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Silicon CMOS architecture for a spin-based quantum computer

M. Veldhorst, H. G. J. Eenink, C. H. Yang, A. S. Dzurak

arXiv:1609.09700v1cond-mat.mes-hallquant-ph

TL;DR

Large-scale quantum computing requires scalable qubit control alongside quantum error correction, but the classical-quantum interface remains underdeveloped. This paper proposes a CMOS-compatible silicon architecture using transistor control, exchange-coupled quantum-dot spins, ESR control, and dispersive readout, with surface-code operation and estimated unit-cell dissipation of approximately 50 nW. The architecture is intended to scale from 480-qubit modules toward thousands or millions of qubits, subject to continued CMOS improvements and manufacturing challenges.

  • Problem

    The classical-quantum interface for scaling quantum computers to very large qubit numbers remains underdeveloped despite progress in QEC and high-fidelity qubits.

    Source: II.b. Surface code operations · p. 3, §IV · p. 5

  • Method

    The paper proposes a CMOS-compatible silicon architecture integrating transistor control, floating-gate tuning, exchange-coupled quantum-dot spins, ESR control, and gate-based dispersive readout.

    Source: §I · p. 1, §II · p. 3, II.a. Gate-based dispersive readout… · p. 3

  • Results

    The architecture supports surface-code operations, scales through 480-qubit modules, and has an estimated dynamic dissipation of approximately 50 nW per surface-code unit cell.

    Source: II.b. Surface code operations · p. 4, §III · p. 5, §IV · pp. 5–6

  • Takeaways & Limitations

    The design provides a proposed route toward silicon quantum processors containing thousands to millions of qubits using scalable control lines and global qubit control.

    Source: §IV · pp. 5–6

    The architecture requires multiple transistors per qubit, significantly challenging CMOS manufacturing capabilities and continued device down-scaling.

    Source: §IV · p. 6

Abstract

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Recent advances in quantum error correction (QEC) codes for fault-tolerant quantum computing \cite{Terhal2015} and physical realizations of high-fidelity qubits in a broad range of platforms \cite{Kok2007, Brown2011, Barends2014, Waldherr2014, Dolde2014, Muhonen2014, Veldhorst2014} give promise for the construction of a quantum computer based on millions of interacting qubits. However, the classical-quantum interface remains a nascent field of exploration. Here, we propose an architecture for a silicon-based quantum computer processor based entirely on complementary metal-oxide-semiconductor (CMOS) technology, which is the basis for all modern processor chips. We show how a transistor-based control circuit together with charge-storage electrodes can be used to operate a dense and scalable two-dimensional qubit system. The qubits are defined by the spin states of a single electron confined in a quantum dot, coupled via exchange interactions, controlled using a microwave cavity, and measured via gate-based dispersive readout \cite{Colless2013}. This system, based entirely on available technology and existing components, is compatible with general surface code quantum error correction \cite{Terhal2015}, enabling large-scale universal quantum computation.

I. PHYSICAL ARCHITECTURE

The proposed physical architecture vertically integrates a silicon-28 quantum layer with CMOS transistors and scalable interconnections. A 480-qubit module provides the repeating unit for larger processors, although further CMOS down-scaling remains necessary.

I. PHYSICAL ARCHITECTURE

  • An SOI wafer places the isotopically enriched silicon-28 2D qubit array beneath a transistor layer, interconnected through polysilicon vias.Source: §I · p. 1, Figure 1 · p. 2
  • At a 7nm feature size, the minimum qubit size is approximately 63 nm × 63 nm, consistent with experimental silicon quantum dot qubits.Source: §I · p. 1
  • Fabricating the assumed classical devices requires continued advances in semiconductor down-scaling.Source: §I · pp. 1–2
  • The control architecture uses vertically stacked interconnection layers to reconcile the different geometries of classical and quantum circuits.Source: §I · p. 2
  • A 480-qubit module forms the point beyond which scaling becomes straightforward replication of the same structure.Source: §I · p. 2, Figure 1 · p. 2

II. ELECTRICAL OPERATION

The electrical design loads and calibrates single-electron spin qubits in quantum dots, using floating gates, exchange coupling, and globally broadcast control for surface-code operation.

II. ELECTRICAL OPERATION

  • Each quantum dot receives one electron through word- and bit-line addressing, while gate-based dispersive readout verifies occupancy.Source: §II · p. 3
  • The complete structure operates at approximately 1 K or below inside an ESR cavity that applies qubit-control pulses.Source: §II · p. 3
  • Floating memory gates tune each qubit's resonance frequency through electrical g-factor control, with six resonance frequencies required for the surface code.Source: §II · p. 3
  • Q-gates are calibrated so adjacent exchange is negligible when J-gates are off and common when J-gates are on.Source: §II · p. 3
  • Global parallel control is treated as crucial for large-scale operation.Source: §II · p. 3

II.a. Gate-based dispersive readout and initialization

The architecture proposes Pauli spin blockade with gate-based dispersive readout for parity measurements between single-spin qubits. Row-wise frequency-multiplexed readout is designed to operate within silicon-spin coherence times.

II.a. Gate-based dispersive readout and initialization

II.b. Surface code operations

The proposed spin-qubit surface code uses six-qubit unit cells and an addressing protocol compatible with individual, row-wise, and global operations. The work focuses on realizing the array rather than calculating implementation-specific error thresholds.

II.b. Surface code operations

III. HEAT DISSIPATION

The architecture estimates dynamic dissipation from J-gates and considers cooling constraints from stacked addressing lines. The estimated dissipation and thermal conductivity suggest operation above approximately 0.1 K is feasible.

Power estimate

  • Dynamic power from a surface-code unit cell is modeled as P = CV^2αf, where capacitance, voltage, activity, and clock frequency determine dissipation.The estimate focuses on J-gates as likely the largest dissipation source.Source: §III · p. 5
  • V = 0.2 V gives approximately 50 nW power dissipation for a single surface-code unit cell.The floating-gate thermal fluctuation scale is estimated as kBT/C ≈ 1 µV.Source: §III · p. 5

Cooling constraints

  • Ten to twenty stacked metallic layers are estimated to keep total addressing-line thickness below 5 µm.Cooling power is ultimately limited by thermal conductivity in the upper addressing layers.Source: §III · p. 5
  • Polysilicon thermal conductivity near zero Kelvin is estimated at κ = 100 W/m/K, with sufficient cooling power available above approximately 0.1 K.Lower operation voltage or single-electron-transistor operation could further reduce required cooling power.Source: §III · p. 5

IV. DISCUSSION

The proposed architecture combines scalable control lines, ESR control, exchange coupling, and dispersive readout for surface-code operation. It targets scaling from thousands to millions of qubits, while current CMOS fabrication remains a major constraint.

Architecture and scalability

  • The architecture uses scalable control lines for single-electron spins in isotopically purified silicon and supports surface-code operations through ESR control, exchange coupling, and dispersive readout.The design is intended to scale to thousands or even millions of qubits.Source: §IV · pp. 5–6
  • Global qubit control could address many qubits within their coherence time.This is identified as a key advantage of the proposed design.Source: §IV · p. 6

Limitations

  • Multiple transistors per qubit significantly challenge current CMOS manufacturing capabilities.More uniform qubits could reduce tuning circuitry and floating gates, while low magnetic fields could remove the need for g-factor tuning but restrict single-qubit gates to global operation.Source: §IV · p. 6

Platform scope

  • The architecture is generic across several silicon spin-qubit platforms and qubit types, while requiring only local exchange interaction in the considered system.Potential platforms include Si/SiO2, Si/SiGe, single-spin, singlet-triplet, exchange-only, and hybrid qubits.Source: §IV · p. 6

VI. AUTHOR CONTRIBUTIONS

The authors describe distinct contributions to floating-gate design, universal-computation compatibility, project supervision, and manuscript preparation.

Contributions

  • M. V. and C.H.Y. designed floating gates addressed via vertical transistors above the qubit plane.Source: §VI · p. 6
  • H.G.J.E. and M.V. made the design compatible with universal quantum computation.Source: §VI · p. 6
  • A.S.D. initiated and supervised the project, while all authors contributed to writing the manuscript.Source: §VI · p. 6

Supplementary Information CMOS archictecture for a 2D array of spin qubits

The supplementary architecture develops scalable CMOS control structures for two-dimensional quantum-dot arrays and maps them onto surface-code operation. It covers physical layout, qubit control, readout, and gate implementation.

CMOS control layout

  • A single control structure has aspect ratio 4λ×20λ and is extended to match square qubit arrays and surface-code layouts.The resulting layouts address 20×4 and then 24×20 qubit arrays.Source: Supplementary Information CMOS… · p. 8
  • The basic scalable unit consists of one qubit and two J-gates in a nearest-neighbour-coupled two-dimensional quantum-dot array.The control element uses transistor switches to activate lines, with feature size represented by λ.Source: Figure 4 · p. 8, Figure 5 · p. 9

Array scaling

  • The architecture scales from the elementary control structure to 4×20 and 24×20 arrays containing 80 and 480 qubits.The 480-qubit array is organized to match Data, Word, and Bit lines for surface-code operation.Source: Figure 6 · p. 9, Figure 7 · p. 10

Initialization and readout

  • Qubit initialization and readout use spin-to-charge conversion, with Pauli spin blockade offering higher readout fidelity and avoiding a large reservoir or magnetic field.Single spins can be projected onto singlet-triplet states using a neighbouring reference dot for parity measurement.Source: Supplementary Information CMOS… · p. 11

Qubit operations

  • Single-qubit operations use six resonance frequencies with global cavity control and electrical individual tuning.The frequency groups correspond to Z, data, and X qubits in the surface-code structure.Source: Supplementary Information CMOS… · p. 11
  • Two-qubit gates arise from electrically controlled tunnel coupling or detuning, producing SWAP or CPHASE operations through interaction-dependent phases.Surface-code CNOT operations are implemented with CPHASE and single-qubit pulses, with reference qubits supporting readout.Source: Supplementary Information CMOS… · p. 11

Surface-code operation

  • Surface-code cycles on the two-dimensional quantum-dot array combine CPHASE operations, Hadamard-like pulses, initialization, and readout.Additional z rotations from CPHASE operations are incorporated into the Hadamard-like operation.Source: Supplementary Information CMOS… · p. 11, Figure 8 · p. 12

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