Source-linked AI summary
Stochastic p-bits for Invertible Logic
Kerem Yunus Camsari, Rafatul Faria, Brian M. Sutton, Supriyo Datta
TL;DR
The paper asks whether stochastic units can replace deterministic logic elements while providing accurate Boolean computation and inverse operation. It models tunable p-bits, derives Boltzmann-machine designs for truth tables, and composes them through partially directed connections. The resulting networks implement accurate Boolean and arithmetic operations while retaining invertibility, including 32-bit addition and inverted 4-bit multiplication for factorization.
Problem
The paper addresses the lack of stochastic logic units that combine accurate Boolean computation with invertibility, which standard digital circuits do not provide.
Method
The paper models p-bits as tunable stochastic units, maps truth tables to symmetric Boltzmann machines, and combines those machines with partially directed connections.
Results
The networks implement accurate Boolean and arithmetic operations while retaining invertibility, including 32-bit addition and inverted 4-bit multiplication for factorization.
Takeaways & Limitations
Three-terminal tunable random-bit generators can serve as p-bit building blocks, and hybrid reciprocal-directed networks support both digital-like accuracy and inverse operation.
Abstract
from arXiv · showhide
Conventional logic and memory devices are built out of deterministic units such as transistors, or magnets with energy barriers in excess of 40-60 kT. We show that stochastic units, p-bits, can be interconnected to create robust correlations that implement Boolean functions with impressive accuracy, comparable to standard circuits. Also they are invertible, a unique property that is absent in digital circuits. When operated in the direct mode, the input is clamped, and the network provides the correct output. In the inverted mode, the output is clamped, and the network fluctuates among possible inputs consistent with that output. We present an implementation of an invertible gate to bring out the key role of a three-terminal building block to enable the construction of correlated p-bit networks. The results for this implementation agree well with those from a universal model, showing that p-bits need not be magnet-based: any three-terminal tunable random bit generator should be suitable. We present an algorithm for designing a Boltzmann machine (BM) with symmetric connections that implements a given truth table. We then show how BM Full Adders can be interconnected in a partially directed manner to implement large operations such as 32-bit addition. Hundreds of p-bits get precisely correlated such that the correct answer out of 2^33 possibilities can be extracted by looking at the mode of a number of time samples. With perfect directivity a small number of samples is enough, while for less directed connections more samples are needed, but even in the former case invertibility is largely preserved. This combination of accuracy and invertibility is enabled by the hybrid design that uses bidirectional units to construct circuits with partially directed connections. We establish this result with examples including a 4-bit multiplier which in inverted mode functions as a factorizer.
I. INTRODUCTION
The paper introduces stochastic p-bits as tunable random units that form correlated, accurate, and invertible Boolean logic networks. It develops suitable hardware principles, a truth-table-to-Boltzmann-machine design method, and partially directed networks for larger arithmetic operations.
- Motivation: P-bits are unstable stochastic units whose correlations can implement precise Boolean functions while supporting inverse operation.Direct mode clamps inputs to obtain outputs; inverted mode clamps outputs and samples consistent inputs.
- P-bit building block: A p-bit is a tunable random-number generator with a sigmoidal time-averaged response, implemented through an input-controlled stochastic output.At zero input, the output is equally likely to be −1 or +1; input bias changes the distribution, and the time average equals tanh(Ii).
- Hardware implementation: PSL requires three-terminal building blocks with transistor-like gain and input-output isolation, although the p-bit need not be magnet-based.Any random signal generator whose randomness is tunable through a third terminal is proposed as a suitable building block.
- Boltzmann machines for invertible Boolean logic: The paper gives a one-shot prescription for converting any Boolean truth table into a symmetric Boltzmann-machine J-matrix without learning.The construction uses bipolar variables, hidden units, and symmetric couplings, with robustness to rounded and relatively sparse interconnections.
- Invertibility: PSL invertibility is a relation inverse: fixing an output makes the network fluctuate among all input combinations consistent with that output.For AND, output 0 corresponds probabilistically to the three input pairs (0,0), (0,1), and (1,0), rather than to a single functional inverse.
- Directed networks of Boltzmann machines: A 32-bit adder converges to the one correct sum out of 2^33 ≈8 billion possibilities when component Boltzmann machines are connected with directed carry couplings.The hybrid design keeps symmetric connections within Full Adders while directing couplings between them, preserving substantial invertibility.
- Directed networks of Boltzmann machines: A 4-bit multiplier operates as a factorizer in inverted mode, demonstrating invertible functionality in a larger composed circuit.The paper presents this example to show how p-bit invertibility can be used across different circuit functions.
II. AN EXAMPLE HARDWARE IMPLEMENTATION OF PSL
The hardware implementation uses stochastic circular nanomagnets with separate READ and WRITE paths, CMOS amplification, and resistor-based interconnections to realize correlated, invertible p-bit logic. Simulations produce sigmoidal responses and support invertible AND-gate operation with low-barrier magnets and tunable spin-current interactions.
- Hardware architecture: The circular magnet has approximately zero thermal energy barrier and can be pinned by a GSHE-generated spin current.Its stochastic magnetization supplies the tunable random behavior required for p-bits.
- Sigmoidal response: A 500 ns time-averaged magnetization versus spin current exhibits the sigmoidal characteristic required for p-bit operation.The response is normalized using the GSHE gain and thermal noise strength; the example uses β≈1.5.
- Sigmoidal response: For the modeled circular magnets, a dimensionless applied spin current of approximately 10 pins magnetization in the ±z directions.The pinning current depends on saturation magnetization and volume for the in-plane magnets considered.
- Current scale: The thermal spin current is estimated at approximately 0.25–2.5 µA, while superparamagnet pinning currents are at least an order of magnitude below stable-magnet switching currents.The paper suggests this scale could support lower-energy stochastic nanomagnet implementations than stable-magnet spin-torque switching.
- Hardware architecture: A three-terminal p-bit separates WRITE biasing from READ sensing, providing gain for fan-out and isolation against read disturb.The implementation uses a GSHE-driven circular magnet, MTJ sensing, and CMOS inverters as a buffer.
- Invertible AND gate: With the AND-gate output clamped to zero, the floating inputs visit the three consistent states (00), (01), and (10) with approximately equal probability.The output is thresholded at VDD/2 and the histogram is formed after 200 ns of simulation.
Detailed Simulation Parameters
The detailed simulations model stochastic circular magnets with the sLLG equation and couple them to CMOS inverter characteristics. The selected parameters define thermal noise, spin-current drive, and signal averaging for the hardware examples.
- Magnet dynamics: The hardware examples use stochastic Landau–Lifshitz–Gilbert dynamics to obtain the magnetization of circular nanomagnets.The model includes damping, spin current, effective fields, demagnetizing fields, and thermal fluctuations.
- Magnet dynamics: The spin current is uniformly distributed over the macrospin, whose spin count is Ni = MsVol./µB.Here µB is the Bohr magneton.
- Simulation procedure: Each sigmoid data point averages the z-component of magnetization for 500 ns with a 0.05 ps time step.The CMOS inverter characteristics and spherical sLLG model are evaluated in a modular HSPICE-based framework.
- CMOS characteristics: The 14 nm FinFET inverter and buffer responses amplify the MTJ signal, while increasing pFET size shifts the buffer response to the required midpoint.At zero GSHE bias, the amplified signal is centered near VDD/2 + VR/2.
III. INVERTIBLE BOOLEAN LOGIC WITH BOLTZMANN MACHINES
The paper gives a one-shot construction of symmetric Boltzmann-machine matrices for Boolean truth tables, then demonstrates correlated, direct, and inverse logic using p-bits.
- Truth Table to J-Matrix: A given truth table is transformed from binary to bipolar variables, augmented with hidden units, and converted into a symmetric J-matrix without learning.The added units ensure the imposed conditions fit an invertible representation; diagonal terms are set to zero in the model.
- Truth Table to J-Matrix: The symmetric J-matrix prescription accounts for non-orthogonal truth-table vectors through a projection matrix and adds hidden units to enlarge the state space.The resulting number of p-bits exceeds the number of truth-table lines.
- Truth Table to J-Matrix: A handle bit distinguishes a truth table from its complement and permits electrical reconfiguration between complementary gates such as AND and OR.The handle bit is biased to suppress the complementary truth table.
- Full Adder: A floating Full Adder using its J-matrix agrees quantitatively with the steady-state Boltzmann distribution, including undesired truth-table peaks.The construction uses auxiliary and handle bits alongside named Full Adder terminals.
- Correlated p-bits: When I0 changes from 0 to 2, an AND network transitions from equal-probability uncorrelated noise to sampling only the truth-table states.The correlated states follow the Boltzmann distribution, with thermal noise occasionally ejecting the system from low-energy states.
- Direct and Inverse Logic: Clamping inputs produces the corresponding output, while clamping an OR output to +1 yields three possible input combinations consistent with that output.The inverse operation samples multiple solutions rather than requiring a single functional inverse.
IV. DIRECTED NETWORKS OF BOLTZMANN MACHINES
To scale Boltzmann-machine logic, the paper combines individually symmetric Full Adders with directed carry connections between successive stages.
- Partially Directed Networks: Reciprocal connections within each Full Adder can interfere with the directed computation needed when composing larger circuits.The paper therefore uses a hybrid interconnection strategy rather than fully reciprocal coupling across the whole network.
- Partially Directed Networks: In a 32-bit adder, each Full Adder remains a symmetric Boltzmann machine while carry coupling is non-zero only from the less significant stage to the more significant stage.This partially directed connection distinguishes the composed circuit from the reciprocal behavior of an individual Boltzmann machine.
32-bit Adder/Subtractor
The hybrid p-bit 32-bit adder combines Boltzmann-machine Full Adders with directed or partially directed carry connections to achieve accurate addition and inverse operation. Directivity accelerates convergence, while bidirectionality preserves invertibility at the cost of more samples or longer delays.
- 32-bit Adder/Subtractor: A 32-bit adder extracts the correct 33-bit sum from approximately 2^33 possibilities despite large stochastic fluctuations.At I0 = 1, the correct answer has approximately 12% probability, while larger I0 values can approach 100%; majority voting over T=100 samples extracts the answer.
- 32-bit Adder/Subtractor: The adder also operates inversely: clamping S makes A and B fluctuate in correlated combinations whose sum is sharply peaked at S.This inverse behavior distinguishes the p-bit adder from standard digital circuits.
- 32-bit Adder/Subtractor: Worst-case ripple-carry delay grows linearly as O(n), whereas random inputs produce a logarithmic delay increase.The delay is measured as the time to reach the mode of the array for T=200; each point averages 500 trials, with the mode matching the arithmetic sum.
- 32-bit Adder/Subtractor: The hybrid design achieves digital accuracy because each Full Adder is a Boltzmann Machine while carry connections are directed.For I0 increased from 0.25 to 5, S−A−B equals zero in all 1000 trials in the directed implementation.
- 32-bit Adder/Subtractor: Fully directed carry connections work for addition and subtraction and for clamping least-significant bits, but not most-significant bits.The authors attribute this boundary to controlling information flow upstream rather than downstream.
- 32-bit Adder/Subtractor: Large bidirectionality can still yield correct operation, but directionality, interaction strength, and sample count jointly determine convergence and error.A two-p-bit analysis links the slow decay of a near-unit eigenvalue to bidirectionality; full directivity sets that eigenvalue to zero but can reduce invertibility.
4-Bit Multiplier / Factorizer
The paper uses a 4-bit multiplier in reverse as a probabilistic factorizer: clamping the product causes input bits to fluctuate among consistent factors. The demonstration establishes functionality but not practical-scale factorization.
- 4-Bit Multiplier / Factorizer: A reversed 4-bit multiplier performs integer factorization by clamping its output and allowing the input terminals to produce consistent factors.The multiplier retains directed carry connections and directed connections from Full Adders to AND gates so information flows from output to input.
- 4-Bit Multiplier / Factorizer: For output 9, both inputs settle to 3, while output 6 produces fluctuations between factors 2 and 3.Other products can expose multiple solutions, including both orderings for 3 and several solutions for zero.
- 4-Bit Multiplier / Factorizer: The 4-bit encoding excludes factors such as 9 × 1 for product 9 because the input terminals have only 2 bits.The available factor pairs are therefore constrained by the circuit’s input representation.
- 4-Bit Multiplier / Factorizer: The circuit is sensitive to the relative coupling strengths within AND gates, between AND gates and Full Adders, and to the annealing profile.These sensitivities affect the factorizer’s behavior in the demonstrated implementation.
- 4-Bit Multiplier / Factorizer: Designing practically relevant factorizers is outside the paper’s scope.The demonstration is presented mainly to show how p-bit invertibility can support unusual circuit functions.
V. SUMMARY
The paper presents p-bits as stochastic hardware units for accurate Boolean logic with invertibility, using Boltzmann-machine gates and directed or partially directed interconnections. Demonstrations include a 32-bit adder and reverse multiplication for factorization.
- V. SUMMARY: Probabilistic spin logic uses stochastic p-bits to implement Boolean functions accurately while retaining invertibility absent from deterministic digital circuits.In inverse operation, clamped outputs yield fluctuations among consistent inputs.
- V. SUMMARY: A stochastic nanomagnet implementation illustrates why scalable correlated p-bit networks require three-terminal building blocks.The nanomagnet realization is one possible implementation rather than the only permitted technology.
- V. SUMMARY: The paper gives a one-shot algorithm for converting Boolean truth tables into Boltzmann machines with relatively sparse and quantized symmetric connections.The resulting gates support both direct functions and their probabilistic relation inverses.
- V. SUMMARY: A hybrid 32-bit adder achieves digital accuracy across interaction strength, directionality, and sample-count settings while preserving some invertibility.Even with J12 = 0.75×J21, it selects the correct answer from nearly 2^33 possibilities, though more samples may be required.