Source-linked AI summary
Neuromorphic Silicon Photonic Networks
Alexander N. Tait, Thomas Ferreira de Lima, Ellen Zhou, Allie X. Wu, Mitchell A. Nahmias, Bhavin J. Shastri, Paul R. Prucnal
TL;DR
The paper addresses how silicon photonics can implement reconfigurable neuromorphic computation with a mathematically defined relationship to neural-network models. It demonstrates bifurcation-based isomorphism between a modulator-based broadcast-and-weight circuit and a CTRNN, then programs a simulated 24-neuron network for differential-system emulation. The benchmark predicts a 294× speedup over a verified CPU implementation, while accuracy benchmarking remains difficult for chaotic dynamics.
Problem
The work addresses the need for standardized links between photonic device physics and computational neural-network models, particularly for scalable neuromorphic silicon photonics.
Method
The authors implement a reconfigurable broadcast-and-weight silicon photonic network with microring weights and modulator neurons, and test its CTRNN isomorphism through cusp and Hopf bifurcation observations.
Results
294× acceleration is predicted for a simulated 24-modulator-neuron photonic CTRNN emulating a differential system against a verified CPU benchmark.
Takeaways & Limitations
The demonstrated isomorphism supports using neural-network abstractions and existing CTRNN algorithms to program and benchmark larger silicon photonic systems.
Takeaways & Limitations
Chaotic Lorenz dynamics make emulation-accuracy benchmarking difficult, despite reproduction of qualitative Lorenz behavior by both implementations.
Abstract
from arXiv · showhide
Photonic systems for high-performance information processing have attracted renewed interest. Neuromorphic silicon photonics has the potential to integrate processing functions that vastly exceed the capabilities of electronics. We report first observations of a recurrent silicon photonic neural network, in which connections are configured by microring weight banks. A mathematical isomorphism between the silicon photonic circuit and a continuous neural network model is demonstrated through dynamical bifurcation analysis. Exploiting this isomorphism, a simulated 24-node silicon photonic neural network is programmed using "neural compiler" to solve a differential system emulation task. A 294-fold acceleration against a conventional benchmark is predicted. We also propose and derive power consumption analysis for modulator-class neurons that, as opposed to laser-class neurons, are compatible with silicon photonic platforms. At increased scale, Neuromorphic silicon photonics could access new regimes of ultrafast information processing for radio, control, and scientific computing.
RESULTS
The silicon photonic circuit reproduces key bifurcations of a continuous-time recurrent neural network, supporting a dynamical isomorphism. A simulated 24-node photonic CTRNN emulates a differential system with predicted acceleration and quantified hardware requirements.
- Network model: The CTRNN is modeled as ordinary differential equations coupled through a recurrent weight matrix.The physical implementation uses microring transmission weights, Mach–Zehnder modulator transfer functions, and modulator voltages as neuron states.
- Cusp bifurcation: The single-node device experimentally reproduces pitchfork, bistable, and cusp bifurcations predicted by the model.The fitted model places the cusp point at WB = 0.54; non-idealities are attributed to hard saturation at high input voltage and feedback weight.
- Hopf bifurcation: The two-node network exhibits a Hopf bifurcation, with oscillations above threshold in the 1–5 kHz range and model agreement away from the transition regime.The fitted bifurcation occurs at WB = .48, and the frequency axis is normalized to a boundary frequency of 4.81 kHz.
- Hardware metrics: The proposed 24-neuron implementation requires 24 laser wavelengths, 24 modulators, and 576 microring weights, with an expected minimum total power of 106 mW.The predicted computational efficiency is 180 fJ/SOP at 1 GHz bandwidth, and the weight-bank area is 0.36 mm^2.
- Scope and limitations: Benchmarking emulation accuracy is difficult because the Lorenz attractor is chaotic, motivating future non-chaotic ODE or CPG benchmarks.The paper notes that qualitative Lorenz behavior is reproduced but does not provide a straightforward accuracy comparison.
DISCUSSION
The work establishes integrated neuromorphic silicon photonics as a reconfigurable analog computing platform and evaluates its broader significance. It connects experimental neuromorphic behavior with task-oriented programming, benchmarking, silicon compatibility, and potential application areas.
- Implications: The demonstrated isomorphism supports task-oriented programming and benchmark analysis for analog photonic processors.The authors describe these analyses as tools for assessing analog photonic processors against conventional processors across application domains.
- Silicon compatibility: Modulator-class neurons are silicon-compatible and retain the repertoire of continuous-time recurrent neural network functions.The paper contrasts them with laser-class neurons, which offer richer spiking dynamics but face integration and networking challenges.
- Relation to prior work: The work is the first demonstration of an integrated recurrent weight network, extending prior photonic neural-network research beyond isolated neurons and fixed chains.Earlier systems included individual laser neurons, fixed cascadable chains, and recurrent neural networks implemented in fiber.
- Relation to prior work: Neuromorphic and reservoir approaches differ fundamentally: neuromorphic systems establish an isomorphism with a neural model, whereas reservoir methods learn desired behavior from complex dynamics.The paper presents the two approaches as complementary rather than interchangeable.
- Potential applications: At increased scale, neuromorphic silicon photonics could address scientific-computing and RF-signal-processing problems while leveraging existing algorithms.The discussion specifically connects continuous-time recurrent and Hopfield networks with mathematical programming, optimization, and RF applications.
- Results and outlook: A 24-modulator-neuron simulation estimated a 294× speedup over a verified CPU benchmark, while experiments observed network-mediated cusp and Hopf bifurcations.These results combine a task-level performance estimate with proof-of-concept dynamical behavior in an integrated broadcast-and-weight system.
METHODS
The methods combine calibrated microring weight banks, modulator-neuron simulations, and benchmarking procedures to evaluate recurrent photonic CTRNNs and their power requirements.
- Photonic network preparation: The integrated network is calibrated offline for thermo-optic cross-talk and filter-edge transmission before users specify a desired weight matrix.Electrical feedback is disabled during calibration, and a control model calculates and applies the requested weights afterward.
- Photonic network preparation: Weighted optical outputs are detected off-chip, low-pass filtered at 10kHz, and used to drive fiber Mach-Zehnder modulator neurons.Filtering suppresses delayed dynamics that would interfere with CTRNN analysis in the off-chip-neuron setup.
- Photonic CTRNN solver: The simulated photonic CTRNN uses modified NEF compilation with sinusoidal MZM tuning curves, unit-square encoders, and Fourier-based gains and offsets.The construction uses 4 encoders, 3 gain frequencies, and 2 offsets, producing 24 modulator neurons.
- Photonic CTRNN solver: 24 modulator neurons are sufficient for the compiled representation, although neurons with negligible activity could be pruned after compiling the weight matrix.The proposed pruning is an optimization rather than part of the reported 24-neuron configuration.
- Conventional CPU solver: The CPU benchmark uses Euler continuation, with measured step time ∆t = 24.5 ± 1.5ns and less than 1% divergence probability for γ_CPU/∆t ≥150.The model accounts for floating-point operations and cache accesses, and the empirical measurement validates its timing estimate.
- Power and scaling analysis: Signal cascadability requires round-trip gain g ≥1; otherwise recurrent signals attenuate and system eigenvalues cannot have positive real parts.For voltage-mode modulators, increasing receiver impedance raises gain but lowers bandwidth according to f = (2πR_rC_mod)^−1.
- Power and scaling analysis: A typical silicon photonic platform yields a minimum pump power of 2.2 × 10^−13 W/Hz, while the 24-node 1GHz design requires 0.22 mW/neuron and 106 mW wall-plug power.The 1GHz restriction is used to avoid time-delay dynamics.