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A microprocessor based on a two-dimensional semiconductor
Stefan Wachter, Dmitry K. Polyushkin, Ole Bethge, Thomas Mueller
TL;DR
The paper analyzes an inverter input-output characteristic using long-channel FET theory. It models the pull-down transistor in saturation and the load transistor in the sub-threshold regime, while showing that equal transistor ratios reduce the switching threshold below 1 V but produce low noise margin.
Problem
The inverter input-output characteristic requires analytic modeling based on long-channel FET theory.
Method
The analysis models the pull-down FET in saturation and the load FET in the sub-threshold regime, where it acts as a current source.
Results
Below 1 V, the switching threshold falls when both transistors use the same ratio, resulting in low noise margin.
Takeaways & Limitations
Equal transistor ratios trade a lower switching threshold for low noise margin, especially with additional hysteresis.
Takeaways & Limitations
The model parameters are taken from the experiment shown in Figure 2b.
Abstract
from arXiv · showhide
The advent of microcomputers in the 1970s has dramatically changed our society. Since then, microprocessors have been made almost exclusively from silicon, but the ever-increasing demand for higher integration density and speed, lower power consumption and better integrability with everyday goods has prompted the search for alternatives. Germanium and III-V compound semiconductors are being considered promising candidates for future high-performance processor generations and chips based on thin-film plastic technology or carbon nanotubes could allow for embedding electronic intelligence into arbitrary objects for the Internet-of-Things. Here, we present a 1-bit implementation of a microprocessor using a two-dimensional semiconductor - molybdenum disulfide. The device can execute user-defined programs stored in an external memory, perform logical operations and communicate with its periphery. Importantly, our 1-bit design is readily scalable to multi-bit data. The device consists of 115 transistors and constitutes the most complex circuitry so far made from a two-dimensional material.
METHODS
The microprocessor was fabricated from a large-area MoS2 film transferred onto a target wafer, then patterned into gated and contacted devices. External electronics supplied clock and memory signals for testing.
- METHODS: The device stack used electron-beam-patterned Ti/Au gate metal, a 22-nm Al2O3 gate oxide, and etched via-holes between metal layers.The oxide was deposited by atomic layer deposition, and potassium hydroxide etching defined the via-holes.
- METHODS: A large-area MoS2 film was grown by chemical vapor deposition on sapphire and transferred onto the target wafer.The film covered approximately 50 mm2 and was mainly bilayer, with small multilayer islands and contaminations.
- METHODS: Rectangular MoS2 channels were patterned and etched with Ar/SF6 plasma before top Ti/Au contacts were deposited.The top contacts used Ti/Au with thicknesses of 5/35 nm.
- METHODS: Vacuum annealing at 400 K for several hours removed adsorbates and reduced device hysteresis.An oxygen-plasma treatment was also used to remove polymer-mask residue before top-metal formation.
- METHODS: Clock signals and external-memory behavior were generated with a computer digital I/O card, while waveforms were recorded using a semiconductor parameter analyzer.The device was supplied with a 5 V operating voltage during testing.
Supplementary Information for
The supplementary information describes analytical modeling of the MoS2 inverter and supporting device and circuit characterization. It also documents how asymmetric transistor sizing improves switching behavior and noise margin relative to a symmetric design.
- Supplementary Information for: The supplementary circuit schematic provides the detailed implementation of the MoS2 microprocessor introduced in the paper.The main text identifies the work as a complex digital circuit implemented with a two-dimensional semiconductor.
- Supplementary Information for: The supplementary figures document MoS2 growth, FET characteristics, transfer curves for asymmetric and symmetric designs, and device operation at 50 Hz.The growth characterization distinguishes triangular monolayers near sample edges from continuous polycrystalline bilayer film toward the center.
- Supplementary Information for: Analytical inverter modeling used long-channel FET theory, with the pull-down FET in saturation and the load FET operating in sub-threshold.The sub-threshold load transistor acts as a current source over a large drain-voltage range.
- Supplementary Information for: The inverter model relates its currents and voltage characteristics using experimentally determined device parameters.The parameters were taken from the experimental transfer characteristics, and the currents were equated to obtain a relation between voltages.
- Supplementary Information for: Equal transistor sizing lowers the switching threshold below 1 V and produces a low noise margin, especially when additional hysteresis is present.This behavior is reported for the symmetric design in contrast with the asymmetric design.