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Fabrication-constrained nanophotonic inverse design
Alexander Y. Piggott, Jan Petykiewicz, Logan Su, Jelena Vučković
TL;DR
Fabricability limits the practical use of computationally designed nanophotonic devices. The paper introduces inverse design with curvature-based fabrication constraints and demonstrates several devices, including an experimentally validated broadband 1 × 3 splitter. Averaged over 1400–1700 nm, the splitter achieved measured insertion loss of 0.642 ± 0.057 dB and power uniformity of 0.641 ± 0.054 dB.
Problem
Computationally designed nanophotonic structures can contain features that are difficult to resolve with industry-standard optical lithography.
Method
The paper incorporates fabrication constraints into inverse design by imposing curvature constraints on dielectric boundaries and handling narrow gaps or bridges with morphological operations.
Results
0.642 ± 0.057 dB measured insertion loss and 0.641 ± 0.054 dB power uniformity were achieved by the 1 × 3 splitter averaged over 1400–1700 nm.
Takeaways & Limitations
The demonstrated devices have no small features that would be difficult to resolve with photolithography, supporting practical inverse-designed integrated-photonics components.
Abstract
from arXiv · showhide
A major difficulty in applying computational design methods to nanophotonic devices is ensuring that the resulting designs are fabricable. Here, we describe a general inverse design algorithm for nanophotonic devices that directly incorporates fabrication constraints. To demonstrate the capabilities of our method, we designed a spatial-mode demultiplexer, wavelength demultiplexer, and directional coupler. We also designed and experimentally demonstrated a compact, broadband $1 \times 3$ power splitter on a silicon photonics platform. The splitter has a footprint of only $3.8 \times 2.5~\mathrm{μm}$, and is well within the design rules of a typical silicon photonics process, with a minimum radius of curvature of $100~\mathrm{nm}$. Averaged over the designed wavelength range of $1400 - 1700~\mathrm{nm}$, our splitter has a measured insertion loss of $0.642 \pm 0.057 ~\mathrm{dB}$ and power uniformity of $0.641 \pm 0.054~\mathrm{dB}$.
I. INTRODUCTION
Computational nanophotonic designs can outperform traditional structures but often contain features that are difficult to fabricate. The paper addresses this by combining level-set inverse design with curvature-based fabrication constraints and topology cleanup.
- I. INTRODUCTION: Full-space optimization can produce higher-performance, smaller-footprint nanophotonic devices than hand-tuned analytical designs.
- I. INTRODUCTION: Fabricating arbitrary-topology designs remains challenging because features resolved by electron-beam lithography may be difficult to resolve with optical lithography.
- I. INTRODUCTION: The proposed inverse design method imposes curvature constraints on dielectric boundaries to achieve an approximate minimum feature size.
- I. INTRODUCTION: A level-set representation places material boundaries at φ = 0 and handles topology changes such as merging and splitting of holes.
- I. INTRODUCTION: Gradient descent minimizes the electromagnetic objective, with gradients efficiently computed using adjoint sensitivity analysis.
- I. INTRODUCTION: Curvature filtering smooths regions above the allowable curvature, while morphological operations detect and remove narrow gaps or bridges.
III. DESIGNED DEVICES
The method was applied to several silicon-photonics devices, including a broadband 1 × 3 splitter designed under explicit curvature and performance constraints. Its optimization converged from a star-shaped geometry in 18 iterations, and the resulting structure resembled a boundary-optimized MMI.
- III. DESIGNED DEVICES: The demonstrated devices use a fully etched 220 nm silicon layer with SiO2 cladding on a silicon photonics platform.
- III. DESIGNED DEVICES: 18 iterations were required for splitter optimization, totaling 216 electromagnetic simulations across six design wavelengths.
- III. DESIGNED DEVICES: The optimized splitter appeared to operate using the multi-mode interferometer principle, despite no human input during design.
B. Spatial mode demultiplexer
The spatial-mode demultiplexer routes two higher-order input modes to separate fundamental-mode outputs under broadband efficiency and crosstalk constraints. Its simulated design achieved low insertion loss and high contrast across 1400–1700 nm.
- B. Spatial mode demultiplexer: The demultiplexer routes TE10 and TE20 modes from a 750 nm input waveguide to fundamental TE modes in two 400 nm output waveguides.
- B. Spatial mode demultiplexer: 0.826 dB average insertion loss and contrast better than 16 dB were simulated across the 1400–1700 nm design bandwidth.
C. Wavelength demultiplexer
The wavelength demultiplexer is a compact three-channel device designed with fabrication constraints and 40 nm channel spacing. Simulations show approximately 1.5 dB insertion loss, better than 16 dB contrast, and usable bandwidth above 10 nm per channel.
- The device is a three-channel wavelength demultiplexer with 40 nm channel spacing and 500 nm-wide input and output waveguides.
- A 40 nm minimum radius of curvature and 90 nm minimum gap or bridge width were enforced during design.
- Approximately 1.5 dB insertion loss was achieved at each channel center, with contrast better than 16 dB.
- Each wavelength channel has a usable bandwidth greater than 10 nm.
- The paper demonstrates this device alongside spatial-mode demultiplexers, directional couplers, and a broadband 1 × 3 splitter.
A. Fabrication
The splitter was fabricated on a 220 nm silicon-on-insulator device layer and characterized by edge coupling with lensed fibers. Measurements broadly matched simulations, while fabrication-related spectral shifts were attributed to slight etching errors.
- The splitter was fabricated on SOI wafers with a nominal 220 nm device layer and 3.0 µm buried oxide layer.
- A 330 nm ZEP-520A resist layer was patterned by electron-beam lithography and transferred into silicon using plasma etching.
- Transmission was measured by edge-coupling lensed fibers, with polarization-maintaining input fiber used to excite only the TE mode.
- Simulations and measurements matched reasonably well, although measured devices showed slightly higher losses and a spectral shift.
- The measured devices were highly consistent across four samples, indicating robustness to fabrication error.
- 0.642 ± 0.057 dB measured insertion loss and 0.641 ± 0.054 dB power uniformity were obtained over 1400–1700 nm.
V. CONCLUSION
The paper incorporates fabrication constraints into inverse design and applies the method to several compact nanophotonic devices, including an experimentally demonstrated broadband 1 × 3 splitter.
- The method designs spatial-mode and wavelength demultiplexers, a 50-50 directional coupler, and a broadband 1 × 3 splitter.
- The devices have no small features that would be difficult to resolve with photolithography.
- Figure 6 overlays measurements from 4 identically fabricated devices, showing their average, minimum, and maximum performance.
A. Problem description
The design problem specifies desired mode-conversion efficiencies between fixed input and output modes, then seeks fields and permittivity distributions satisfying electromagnetic and output constraints.
- Device functionality is specified by mode conversion efficiency between user-selected input and output modes kept fixed during optimization.
- Each input mode is represented by an equivalent current density, whose electric field satisfies Maxwell’s equations.
- Output-mode amplitudes are constrained between lower and upper bounds using mode orthogonality for guided waveguide modes.
- More generally, output amplitudes are expressed through linear functionals that map electric-field distributions to complex scalars.
- The optimization seeks permittivity and electric fields satisfying the electromagnetic and output constraints while later imposing fabricability constraints on permittivity.
C. Parametrizing the structure
The structure is represented with a two-dimensional level-set function that maps regions to permittivities and supports continuous, curvature-constrained optimization.
- The permittivity is assigned as ϵ1 where φ(x, y) ≤ 0 and ϵ2 where φ(x, y) > 0.
- For numerical optimization, the level-set function is discretized into a two-dimensional array φ ∈ R^U×V.
- A mapping function m parameterizes the discretized level set as the permittivity distribution z.
- Anti-aliasing permits continuous structural variation when level-set boundaries do not align with simulation-grid cells.
- The optimization minimizes a penalty function while enforcing Maxwell’s equations and the level-set parameterization z = m(φ).
- The penalty aggregates violations of field constraints, typically using q = 2 and s = max_i f_i(x_i).
E. Steepest descent optimization
The optimization maintains Maxwell-equation solutions while updating the level-set structure by steepest descent, with gradients computed through adjoint sensitivity analysis.
- The fields and penalty become functions of the level set after Maxwell’s equations are enforced, enabling steepest-descent structure optimization.
- The level set is evolved by advection with a velocity field set equal to the penalty-function gradient.
- Gradient computation differentiates the penalty through the electric fields and permittivity mapping using Wirtinger derivatives for complex variables.
- Differentiating discretized Maxwell’s equations yields the electric-field sensitivity with respect to permittivity.
- Adjoint sensitivity analysis reduces the gradient calculation to a single matrix solve instead of n solves for large n × n matrices.
- The forward and adjoint Maxwell problems can be solved with standard solvers; the implementation uses GPU-accelerated FDFD.
VII. LEVEL SET IMPLEMENTATION
The level-set implementation evolves material boundaries by gradient descent while limiting excessive curvature to promote fabricable geometries. A smoothed weighting function improves convergence when curvature approaches the threshold.
- Curvature limiting: A sharply falling weighting function causes terrible convergence as local curvature crosses κ0, motivating a smoothed weighting function.The smoothing is introduced specifically to improve PDE behavior.
- Curvature limiting: Curvature limiting applies a weighting function to smooth regions whose local curvature exceeds the maximum allowable threshold κ0.The constrained region is defined as points where κ(x, y) > κ0.
- Level-set optimization: Gradient descent evolves the level-set representation φ to minimize an objective describing electromagnetic performance constraints.The boundary motion is represented through a level-set equation for normal-direction updates.
- Numerical implementation: The method discretizes the level-set and curvature equations with Godunov and central-difference schemes, then advances time using Euler’s method.The level-set function is periodically reinitialized as a signed distance function using Russo and Smereka’s scheme.
1 × 3 SPLITTER
The splitter’s fabrication robustness was assessed through etching-error and return-loss simulations. These analyses examine spectral sensitivity and quantify backreflections into supported input-waveguide modes.
- Fabrication robustness: Over-etching and under-etching simulations assess how lateral growth or shrinkage of the splitter design affects transmission spectra.The simulations use finite-difference time-domain calculations over a range of fabrication errors.
- Backreflections: Backreflections into the fundamental TE10 mode remain below 23 dB over the splitter’s operating bandwidth.The simulated return loss is presented in figure S2, and backreflections into the input waveguide comprise only a small fraction of total losses.
- Backreflections: Reflection symmetry makes TE20 backreflections zero and prevents conversion to TM modes, while higher-order-mode scattering is negligible for near-single-mode waveguides.These symmetry and modal conditions limit additional backreflection channels.