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Experimental prototype of a spin-wave majority gate
T. Fischer, M. Kewenig, D. A. Bozhko, A. A. Serga, I. I. Syvorotka, F. Ciubotaru, C. Adelmann, B. Hillebrands, A. V. Chumak
TL;DR
Conventional CMOS scaling motivates beyond-CMOS approaches, including spin-wave logic aimed at low-power information processing. This work experimentally realizes a three-input spin-wave majority gate in a YIG waveguiding structure, showing phase-majority operation and an 11.3 ns prototype switching rise time.
Problem
Increasingly intrinsic limits to conventional CMOS scaling motivate beyond-CMOS devices, while spin-wave logic offers potential low-power operation and majority gates with scaling potential.
Method
The study experimentally investigates a three-input, one-output YIG spin-wave gate that encodes logic in wave phase and combines the inputs through spin-wave interference.
Results
11.3 ns rise time: the prototype switches its output from logic 0 to logic 1, corresponding to an 88.5 MHz potential clock frequency; the output phase follows the majority input phase.
Takeaways & Limitations
The experimental realization supports spin-wave majority gating, with device miniaturization expected to make switching times below 1 ns feasible.
Abstract
from arXiv · showhide
Featuring low heat dissipation, devices based on spin-wave logic gates promise to comply with increasing future requirements in information processing. In this work, we present the experimental realization of a majority gate based on the interference of spin waves in an Yttrium-Iron-Garnet-based waveguiding structure. This logic device features a three-input combiner with the logic information encoded in the phase of the spin waves. We show that the phase of the output signal represents the majority of the phase of the input signals. A switching time of about 10 ns in the prototype device provides evidence for the ability of sub-nanosecond data processing in future down-scaled devices.