Source-linked AI summary
Scalable quantum circuit and control for a superconducting surface code
R. Versluis, S. Poletto, N. Khammassi, N. Haider, D. J. Michalak, A. Bruno, K. Bertels, L. DiCarlo
TL;DR
Scalable fault-tolerant quantum computing requires surface-code processors and control systems that can grow beyond small arrays. The paper proposes a pipelined QEC cycle built from repeating eight-qubit hardware-control cells, fixed frequencies, and detuning sequences, and reports scalability to arbitrary-size fabrics while avoiding unwanted second-order interactions.
Problem
Scaling small quantum processors into large arrays capable of fault-tolerant quantum computation remains an outstanding challenge, including scalable control across the quantum-computer stack.
Method
The scheme combines eight-qubit repeating cells, pipelined X- and Z-type stabilizer measurements, three single-qubit control frequencies, and eight CZf detuning sequences.
Results
Pipelining compresses stabilizer measurements to depth seven and scales without increasing the number of single-qubit frequencies or qubit detuning sequences.
Takeaways & Limitations
The fixed hardware-and-control unit cell provides a basis for spatially multiplexed control of monolithic surface-code fabrics.
Takeaways & Limitations
Fully parallelized CZf implementations require growing detuning resources as fabrics expand and appear practically infeasible by distance five.
Abstract
from arXiv · showhide
We present a scalable scheme for executing the error-correction cycle of a monolithic surface-code fabric composed of fast-flux-tuneable transmon qubits with nearest-neighbor coupling. An eight-qubit unit cell forms the basis for repeating both the quantum hardware and coherent control, enabling spatial multiplexing. This control uses three fixed frequencies for all single-qubit gates and a unique frequency detuning pattern for each qubit in the cell. By pipelining the interaction and readout steps of ancilla-based $X$- and $Z$-type stabilizer measurements, we can engineer detuning patterns that avoid all second-order transmon-transmon interactions except those exploited in controlled-phase gates, regardless of fabric size. Our scheme is applicable to defect-based and planar logical qubits, including lattice surgery.
I. INTRODUCTION
Scaling superconducting processors to fault-tolerant quantum computation remains challenging across hardware and control. The paper proposes a monolithic surface-code scheme combining a repeatable hardware-control unit cell with pipelined stabilizer measurements.
- Surface codes use nearest-neighbor coupling and offer an error threshold near 1% across several error models and decoding strategies.
- Scalable control requires extending a repeatable unit cell into the classical plane to enable spatial multiplexing of signals.
- The proposed scheme uses eight-qubit hardware and control cells, three fixed single-qubit frequencies, and eight detuning sequences for CZf gates.
- Pipelining X- and Z-type stabilizer measurements avoids all second-order transmon interactions except those used for CZf gates, independent of fabric size.
- With CZ gates, Surface-17 requires depth nine and a 740 ns QEC cycle using 20 ns single-qubit gates, 40 ns CZf gates, and 500 ns readout.
B. Limitations of fully parallelized X- and Z-type stabilizer measurements using CZf gates
Fully parallelized X- and Z-type stabilizer measurements are difficult to scale with flux-controlled CZ gates while preserving fixed control resources and operational constraints. The paper addresses this by introducing a pipelined cycle.
- Full parallelization was found unable to satisfy all five desired properties for scalable CZf-based surface-code implementations.
- The desired implementation requires few fixed microwave frequencies, maximal coherence-sweetspot use, safe flux trajectories, fixed detuning resources, and logical-operation compatibility.
- Existing solutions meeting the first three criteria require increasing detuning sequences and ranges as the fabric expands, becoming practically infeasible by distance five.
- The paper therefore introduces pipelined rather than fully parallelized stabilizer measurements to meet the five properties for arbitrary fabric size.
III. THE PIPELINED QEC CYCLE
The pipelined QEC cycle is organized around a small repeatable structure that supports both quantum hardware and control scaling.
- The proposed pipelined QEC cycle combines four key elements for scalable surface-code operation.
- Its first element is an eight-qubit repeating unit cell.
D4 D4 D3
The pipelined design combines repeated eight-qubit cells with a fixed control vocabulary for single-qubit frequencies and CZf detuning sequences.
- Pipelined X- and Z-type stabilizer measurements form one of the scheme’s four core elements.
- Single-qubit control uses three frequencies.
- The required CZf gates use eight detuning sequences realizable by on/off masking of three flux-pulse primitives.
A. Unit cell
The eight-qubit unit cell repeats both the surface-code hardware and coherent control, while pipelining interleaves X- and Z-type stabilizer operations. This reduces circuit depth and preserves fixed control resources as the fabric scales.
- Unit-cell architecture: The eight-qubit unit cell contains four data qubits and four ancillas and is the repeating unit for quantum hardware and coherent control.The fabric can be assembled by repeating and truncating the cell at boundaries.
- Pipelined measurements: Pipelining interleaves coherent operations on one ancilla type with readout of the other type.Single-qubit and two-qubit operations occupy distinct time slots for X- and Z-type stabilizer measurements.
- Measurement slack: Operations such as logical gates, refocusing pulses, or error-correction gates can run during measurement slack without increasing the QEC cycle time.These operations fit into steps C and F while ancillas are measured.
- Scalability: Pipelining compresses stabilizer measurements to depth seven and avoids increasing single-qubit-control frequencies or detuning sequences as the fabric scales.This is two single-qubit-gate steps less than fully parallelized circuits such as the Surface-17 circuit.
C. Single-qubit control and detuning sequences
The control scheme assigns fixed single-qubit frequencies by qubit type and uses qubit-specific detuning sequences during pipelined interactions. The arrangement permits CZ gates at selected frequencies while suppressing unwanted interactions elsewhere.
- Frequency arrangement: Data-qubit single-qubit gates use f1 and f3 in alternating rows, while ancilla gates use the intermediate frequency f2.The unit-cell arrangement uses distinct frequency classes for data and ancilla control.
- Detuning sequences: During interaction steps, D1 and D2, ancillas, and D3 and D4 are pulsed among interaction, control, and parking frequencies according to their roles.The sequences distinguish whether each transmon interacts, idles, or is measured.
- Interaction selectivity: CZ gates occur between transmons at the designated interaction frequencies, while no interactions take place at f1 or the parking frequencies.The selected frequency arrangement hides nonparticipating qubits from one another during the cycle.
D. Constructing detuning sequences by masking of primitive flux pulses
Detuning sequences are generated by masking a small set of reusable flux-pulse primitives. The same masking mechanism also supports selective stabilizer modification and logical-qubit operations.
- Primitive-pulse synthesis: A switch matrix synthesizes interaction-step detuning patterns by on/off masking three flux-pulse primitives.The primitives detune D1/D2, ancillas, and D3/D4 to their respective interaction or parking frequencies.
- Example sequence: For D2, the primitive is enabled at steps 1, 4, 6, and 7 and disabled at steps 2, 3, 5, and 8.This gives a concrete masking pattern for one data-qubit type.
- Turning measurements off: Stabilizer measurements can be fully disabled either by masking an ancilla’s H gates or by masking all interaction-step flux-pulse primitives.The first method preserves decoder tracking of a possible logical operation through ancilla measurements.
- Logical operations: Selective primitive masking removes chosen data qubits from parity checks and can reorder two-qubit gates for operations including defect movement, braiding, and lattice surgery.Removing a D2 qubit from an X-type measurement requires masking its step-1 primitive.
V. IMPLEMENTATION DETAILS AND VARIATIONS
The implementation chooses frequencies around transmon sweet spots while requiring residual interactions to remain tolerable. Under a uniform detuning-scale model, the required detuning depends on gate durations and target error rates.
- Sweetspot considerations: Frequencies are ideally matched to the sweet spots of the corresponding data-qubit groups and ancillas to reduce dephasing from 1/f flux noise.In practice, each group uses the lowest sweetspot frequency among its transmons, with refocusing gates available for nonsweetspot operation.
- Frequency constraints: The frequencies f1, f2, f3, and the parking frequencies must be chosen so residual interactions during single-qubit gates are tolerable.The implementation uses a uniform detuning scale for simplicity.
- Detuning requirement: ξ ∼ 10^-2 or 10^-3 with τ1Q = 20 ns and τ2Q = 40 ns requires ΔF ∼ 400 MHz or 1.2 GHz, respectively.These values state the detuning scale associated with the two target error regimes.
B. Frequency arrangement variations
The alternative frequency arrangement places data qubits at f2 and ancillas at outer frequencies, while still allowing detuning sequences that avert unwanted interactions. The original arrangement is preferable because it gives data qubits more opportunities to remain at their upper frequency, reducing dephasing during coherent steps.
- The alternative arrangement places X1 and Z1 at f1, X2 and Z2 at f3, and data qubits at f2.
- The alternative can use modified detuning sequences to avert all unwanted interactions.
- The original arrangement lets data qubits remain at their upper frequency during all eight interaction steps, compared with only two steps in the flipped arrangement.
- Breaking frequency degeneracies reduces residual single-qubit cross-talk but increases primitive pulses from three to five, or eight when f2 is also split.
C. Switch matrix
The proposed switch matrix must support qubit-specific customization of flux-pulse primitives for timing, amplitude, and frequency-offset adjustments.
- The switch matrix should customize flux-pulse delays, amplitudes, and dc offsets for individual qubits.These controls compensate cable-length mismatch, tune gate and single-qubit phases, and select f1, f2, or f3.
VI. CONCLUSION AND OUTLOOK
The paper combines a repeating eight-qubit hardware-and-control cell with pipelined measurements, fixed frequencies, and reusable detuning sequences. It outlines a Surface-17 cQED realization using dedicated control, bus-resonator coupling, multiplexed readout, and vertical I/O, while noting that cryogenic implementation remains a longer-term goal.
- The scheme repeats an eight-qubit unit cell for both quantum hardware and coherent control.
- It pipelines X- and Z-type stabilizer measurements and uses three fixed single-qubit frequencies with eight detuning sequences composed from three flux-pulse primitives.
- The targeted Surface-17 implementation uses planar cQED, dedicated flux and microwave lines, readout resonators, nearest-neighbor bus resonators, and vertical I/O.
- Frequency-division multiplexing enables simultaneous readout, while spatial multiplexing is intended to reduce microwave-source and control-hardware requirements.
- A cryogenic implementation remains an attractive longer-term direction.