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Neuromorphic Hardware In The Loop: Training a Deep Spiking Network on the BrainScaleS Wafer-Scale System
Sebastian Schmitt, Johann Klaehn, Guillaume Bellec, Andreas Gruebl, Maurice Guettler, Andreas Hartel, Stephan Hartmann, Dan Husmann, Kai Husmann, Vitali Karasenko, Mitja Kleider, Christoph Koke, Christian Mauch, Eric Mueller, Paul Mueller, Johannes Partzsch, Mihai A. Petrovici, Stefan Schiefer, Stefan Scholze, Bernhard Vogginger, Robert Legenstein, Wolfgang Maass, Christian Mayr, Johannes Schemmel, Karlheinz Meier
TL;DR
Analog neuromorphic hardware offers speed and energy advantages but introduces uncontrolled dynamics that complicate deep-network implementation. This paper maps a pretrained network to BrainScaleS and trains it in the loop, restoring hardware performance close to the software model while using approximate gradients.
Problem
Analog neuromorphic hardware can provide speed and energy benefits, but its reduced control over network dynamics and analog variations complicate efficient implementation of contemporary deep neural networks.
Method
The authors convert a pretrained software network into a rate-coded spiking network on BrainScaleS and iteratively update its synaptic parameters using hardware activity and software backpropagation.
Results
After in-the-loop training, hardware accuracy reached 97% ± 2%, close to the software model's 97% accuracy.
Takeaways & Limitations
Approximate gradients, including those computed with a ReLU model, can effectively compensate analog hardware distortions without requiring exact derivatives of spiking activations.
Takeaways & Limitations
The approach was evaluated in an exemplary small-network scenario trained on handwritten digits.
Abstract
from arXiv · showhide
Emulating spiking neural networks on analog neuromorphic hardware offers several advantages over simulating them on conventional computers, particularly in terms of speed and energy consumption. However, this usually comes at the cost of reduced control over the dynamics of the emulated networks. In this paper, we demonstrate how iterative training of a hardware-emulated network can compensate for anomalies induced by the analog substrate. We first convert a deep neural network trained in software to a spiking network on the BrainScaleS wafer-scale neuromorphic system, thereby enabling an acceleration factor of 10 000 compared to the biological time domain. This mapping is followed by the in-the-loop training, where in each training step, the network activity is first recorded in hardware and then used to compute the parameter updates in software via backpropagation. An essential finding is that the parameter updates do not have to be precise, but only need to approximately follow the correct gradient, which simplifies the computation of updates. Using this approach, after only several tens of iterations, the spiking network shows an accuracy close to the ideal software-emulated prototype. The presented techniques show that deep spiking networks emulated on analog neuromorphic devices can attain good computational performance despite the inherent variations of the analog substrate.
I. INTRODUCTION
Analog neuromorphic platforms offer speed and power advantages but introduce dynamic variability that complicates deep-network training. This work trains a BrainScaleS-emulated deep spiking network in the loop using hardware activity and approximate software gradients.
- Analog neuromorphic systems promise lower power consumption and faster operation than conventional simulations while more closely matching biological neural communication.
- Deep spiking networks remain difficult to implement efficiently because analog hardware reduces control over network dynamics and conventional backpropagation requires precise errors.
- The paper trains a deep neural architecture mapped to BrainScaleS using hardware activity and a coarse software model to compute parameter updates.
- The study maps neural-network experiments from abstract descriptions to hardware and evaluates the procedure on handwritten digit recognition.
II. THE BRAINSCALES WAFER-SCALE SYSTEM
BrainScaleS uses analog circuits for continuous-time neuron and synapse dynamics, while spikes are transported digitally across a wafer-scale system. Its hardware scale and analog variability support accelerated computation but impose substantial power and calibration constraints.
- BrainScaleS physically models biological dynamics with analog circuits operating in continuous time rather than numerically simulating them on von Neumann hardware.
- The wafer contains 384 HICANN chips, each hosting 512 adaptive exponential integrate-and-fire neurons, with digital packet routing for spikes.
- The system combines analog neuron and synapse dynamics with digital, event-based spike communication and auxiliary hardware for power, control, and analog readout.
- Digital interfaces include 48 FPGAs and Gigabit and 10-Gigabit-Ethernet connections for configuration and spike data.
- A single module has a specified maximum design power of 2 kW, with reported power figures based on this maximum because power management is not currently used.
B. Running Neuronal Network Experiments
BrainScaleS experiments transform abstract neural-network descriptions into calibrated, hardware-compatible configurations. Calibration improves correspondence with model dynamics, but residual analog variation motivates iterative hardware-in-the-loop adjustment.
- The software stack transforms topology, model parameters, and stimuli into hardware-constrained experiment configurations and low-level data.
- PyNN provides the user-facing description, while the transformation maps neurons, routes connections, and translates parameters into hardware settings.
- C. Calibration: Calibration fits each neuron's analog control parameter to a desired synaptic time constant, substantially reducing but not eliminating neuron-to-neuron variation.
- C. Calibration: A calibrated silicon neuron broadly matches NEST under identical parameters and input spikes, although its inhibitory response can remain weaker than simulated.
- Expert users can iteratively modify synaptic weights and input stimuli through low-level settings after hardware access is scheduled.
C. Calibration
Calibration translates desired neuron parameters into hardware controls while accounting for manufacturing variation. It reduces, but does not eliminate, mismatch between calibrated silicon neurons and numerical simulations, motivating hardware-in-the-loop training.
- C. Calibration: Calibration maps target parameters, such as membrane time constants, to corresponding hardware control parameters for each neuron.The mapping rules are obtained per neuron.
- C. Calibration: Hardware time constants are accelerated by 10 000, with 1 µs of hardware time corresponding to 10 ms of emulated biological time.
- C. Calibration: Voltage conversion uses a unit-free scaling factor α and an offset s, with quantities subsequently reported in the biological domain unless stated otherwise.
- C. Calibration: Calibration varies an analog control parameter, measures the resulting synaptic time constant, and fits a mapping from the desired time constant to that control value.This procedure significantly reduces neuron-to-neuron variation, but not perfectly.
- C. Calibration: Despite overall agreement with NEST simulations, calibrated neurons can retain mismatches such as weaker inhibitory responses, making in-the-loop training essential for noise-sensitive networks.Analog parameter storage also causes remaining trial-to-trial variability.
III. TRAINING A DEEP SPIKING NETWORK
The training setup uses a feed-forward network with two hidden layers and converts its software-trained weights to a BrainScaleS LIF network for further hardware-based training. Evaluation uses reduced-resolution MNIST digits from five classes.
- III. TRAINING A DEEP SPIKING NETWORK: The network has 100 input units, two 15-unit hidden layers, and one label unit per digit class.The hidden layers learn features in the input space, while directed-edge weights are learned during training.
- III. TRAINING A DEEP SPIKING NETWORK: The dataset reduces MNIST images from 28 × 28 to 10 × 10 pixels and retains digit classes “0”, “1”, “4”, “6” and “7”.It contains 30 690 training images and 5083 test images.
- III. TRAINING A DEEP SPIKING NETWORK: Training proceeds by software backpropagation, conversion to an appropriately parameterized BrainScaleS LIF network, and subsequent hardware-in-the-loop synaptic training.
- III. TRAINING A DEEP SPIKING NETWORK: Figure 5 depicts the feed-forward topology with one input layer, two hidden layers, and one label layer whose size matches the number of image classes.
- III. TRAINING A DEEP SPIKING NETWORK: Figure 6 contrasts an original MNIST “0” with its reduced-resolution version and shows reduced-resolution examples from the other four classes.
A. Software Model
The software model uses normalized pixel inputs and ReLU units in a feed-forward network. Its weights are initialized from a zero-mean normal distribution before training with TensorFlow.
- A. Software Model: Software training uses a TensorFlow implementation with the network properties specified for the model.
- A. Software Model: Each grayscale pixel value is normalized to a number between 0 and 1 and assigned as the activation of an input unit.
- A. Software Model: A ReLU unit outputs x_k = R(...) with R(a) = max(0, a), summing weighted inputs from the previous layer.
- A. Software Model: Table II reports neuron parameters and typical post-calibration variations used to characterize the hardware model.
- A. Software Model: The initial weights for layer n are drawn from a normal distribution with mean zero and a layer-specific standard deviation.
3) Weights:
The software model trains weights by mini-batch gradient descent with momentum using a cost that combines label error and weight regularization. Updates use fixed learning and momentum parameters with weight clipping.
- 3) Weights:: Weights with magnitudes greater than 2σ_n are dropped and re-picked during initialization or training setup.
- 3) Weights:: Mini-batch gradient descent with momentum minimizes the cost over batches of 100 samples.
- 3) Weights:: The cost function combines squared distance between predicted and true label vectors with a regularization term on the weights.The label-error term rewards correct activity and penalizes incorrect activity.
- 3) Weights:: Weight regularization uses λ = 0.001 to suppress large weights and prevent overfitting.
- 3) Weights:: Each update uses learning rate η = 0.05 and momentum parameter γ = 0.9, with weights clipped to [−1, 1].
B. Neuromorphic Implementation
Input images are converted into Poisson spike trains whose pixel-specific firing rates are scaled to a fixed total input rate, with each pattern followed by a decay interval.
- B. Neuromorphic Implementation: Pixel grayscale values determine the firing rates of the corresponding Poisson input spike trains.The firing rate νp for pixel p is proportional to its grayscale value cp.
- B. Neuromorphic Implementation: 2500 Hz is the targeted total firing rate received by the input layer.Each pattern is presented for 0.9 s, followed by 0.1 s of silence.
2) Hardware Configuration:
The pretrained network is mapped onto BrainScaleS using distributed hardware resources, LIF neurons configured to approximate ReLUs, and quantized signed synaptic weights; training then uses recorded hardware activity for updates.
- 2) Hardware Configuration:: Neurons are randomly placed on 8 HICANNs, with 6 additional chips for input and on-wafer routing across 5 FPGAs.Four hardware neuron circuits are combined into each logical neuron to increase available inputs.
- 2) Hardware Configuration:: LIF neurons are configured to approximate ReLU behavior by retaining thresholding and positive suprathreshold responses while disabling adaptation and exponential features.The mapping uses calibrated neuron parameters despite variation between hardware neurons.
- 2) Hardware Configuration:: Trained artificial weights are converted to 4-bit hardware weights, with positive and negative values assigned to excitatory and inhibitory synapses, respectively.The corresponding synapse of the opposite sign is turned off.
- 2) Hardware Configuration:: Each in-the-loop iteration records hardware activity and uses the measured firing rates to update the LIF network’s synaptic weights.The procedure follows a hardware forward pass and a software-computed backward update.
IV. RESULTS
In-the-loop training largely restores the performance lost during hardware conversion: the spiking implementation approaches the software model’s accuracy, with only slight weight adjustments required.
- IV. RESULTS: After training, all presented digit images are classified correctly except one image of digit “6”, which is mistaken for a “4”.This example uses one choice of hardware neurons and initial software parameters.
- IV. RESULTS: Only slight weight adjustments are needed to compensate for hardware effects.The before-and-after hardware weights are compared in Fig. 8.
- IV. RESULTS: 97% software accuracy after 15,000 training steps falls to 72 +12−2% after conversion, then returns close to software performance after in-the-loop training.The comparison is reported across 130 hardware-neuron and software-initialization conditions, with uncertainty expressed by the interquartile range.
V. DISCUSSION
The discussion frames analog neuromorphic deployment as a mapping-and-robustness problem addressed by hardware-in-the-loop training, while emphasizing that the current evidence is limited to a small proof of principle and software-assisted training.
- V. DISCUSSION: Analog deployment requires mapping abstract network units to spikes and compensating distortions in neuron dynamics and parameters.The BrainScaleS approach maps a pretrained network using rate coding, then applies in-the-loop training.
- V. DISCUSSION: A small handwritten-digit network nearly restores the software model’s performance in hardware using approximate ReLU gradients rather than exact LIF derivatives.This avoids determining exact cost-function derivatives for diverse analog neuron activation functions.
- V. DISCUSSION: The experiments are proof-of-principle commissioning studies, leaving open whether the results extend to larger networks and more complex datasets.The authors identify larger-scale evaluation as the next major question.
- V. DISCUSSION: Fully porting training to hardware remains a future challenge, although an integrated plasticity processor has been designed to support runtime learning rules.The current acceleration benefits operation of trained networks rather than the training process itself.
- V. DISCUSSION: 130-run accuracy curves quantify variability across software initializations and hardware-neuron selections for the software and in-the-loop implementations.The uncertainty is represented by the interquartile range.
- V. DISCUSSION: The authors suggest that hardware training could eventually enable accelerated learning for biologically inspired architectures.They note that such architectures can, in some contexts, outperform classical machine-learning algorithms.