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0.5 Petabyte Simulation of a 45-Qubit Quantum Circuit
Thomas Häner, Damian S. Steiger
TL;DR
Large quantum circuits soon challenge classical simulation, although such simulation remains important for validation, calibration, and benchmarking. The paper combines portable optimized kernels with gate scheduling that reduces communication, achieving a 45-qubit simulation and more than order-of-magnitude time-to-solution improvements. The approach reaches the reported largest quantum circuit simulation while exposing performance limits from communication and memory behavior.
Problem
Near-term quantum computers will soon reach sizes that are difficult to simulate classically, despite the need for simulation in validation, calibration, and benchmarking.
Method
The authors use automatic code generation, optimized multi- and many-core kernels, and circuit clustering to reduce communication during quantum supremacy circuit simulation.
Results
The system simulates 45 qubits on 8,192 Cori II nodes using 0.5 petabytes of memory, with time-to-solution improvements exceeding one order of magnitude across scales.
Takeaways & Limitations
The simulator extends classical quantum-circuit simulation to 45 qubits while improving performance portability across a wide range of processors.
Takeaways & Limitations
The 45-qubit run averaged 0.428 PFLOPS, with communication and synchronization consuming 78% of simulation time.
Abstract
from arXiv · showhide
Near-term quantum computers will soon reach sizes that are challenging to directly simulate, even when employing the most powerful supercomputers. Yet, the ability to simulate these early devices using classical computers is crucial for calibration, validation, and benchmarking. In order to make use of the full potential of systems featuring multi- and many-core processors, we use automatic code generation and optimization of compute kernels, which also enables performance portability. We apply a scheduling algorithm to quantum supremacy circuits in order to reduce the required communication and simulate a 45-qubit circuit on the Cori II supercomputer using 8,192 nodes and 0.5 petabytes of memory. To our knowledge, this constitutes the largest quantum circuit simulation to this date. Our highly-tuned kernels in combination with the reduced communication requirements allow an improvement in time-to-solution over state-of-the-art simulations by more than an order of magnitude at every scale.
1 INTRODUCTION
The paper motivates large-scale quantum circuit simulation for validating, calibrating, and benchmarking near-term quantum devices. It combines optimized kernels with circuit scheduling to simulate larger circuits faster.
- Near-term quantum devices may perform tasks that would require the world’s most powerful supercomputers to reproduce classically.
- Quantum circuit simulators support algorithm verification, noise studies, calibration, benchmarking, and quantum hardware/software co-design.
- Existing simulators primarily target small single-node systems, while prior massively parallel work reached 42 qubits and qHiPSTER reached 42-qubit supremacy circuits.
- The authors combine optimized multi- and many-core kernels with circuit clustering that reduces communication steps and report speedups exceeding one order of magnitude across scales.
- The study simulates a 45-qubit quantum supremacy circuit on Cori II using 0.5 petabytes of memory and 8,192 nodes.
- The benchmark circuits use repeated eight-pattern CZ schedules on a 2D nearest-neighbor architecture, applying all possible two-qubit interactions every eight cycles.
2 BASICS OF QUANTUM COMPUTER SIMULATION
Quantum simulation represents an n-qubit state as a vector with 2^n complex amplitudes and applies gates without explicitly storing the full matrix. This exponential representation makes large simulations memory-intensive.
- A single qubit is a two-level system whose state uses complex amplitudes α_0 and α_1 with normalized probabilities.
- Single-qubit operations are represented by 2 × 2 unitary matrices, including the bit-flip X and Hadamard H gates.
- The controlled-Z gate adds a −1 phase to the |11⟩ basis state and is symmetric between its two qubits.
- Applying a gate to one qubit of an n-qubit state corresponds to multiplying the state vector by a structured sparse operation rather than materializing the full matrix.
- An n-qubit quantum state is represented by a complex vector containing 2^n amplitudes.
- Storing a 50-qubit state vector in double precision would require 16 petabytes of memory.
3 OPTIMIZATIONS
The simulator uses a layered implementation that optimizes gate kernels within a core, scales across a node, and communicates across nodes.
- The simulator combines explicit vectorization, instruction reordering, and blocking to improve single-core quantum gate kernels.
- OpenMP provides intra-node parallelism, while MPI implements inter-node communication for simulations of up to 45 qubits.
3.1 Standard optimizations
Standard simulation avoids explicitly storing exponentially large gate matrices and instead applies their structured action to state vectors. The resulting computation is memory-bandwidth bound on most systems.
- The simulator mimics multiplication by the full gate matrix using structured operations on state vectors instead of storing the matrix.
- A standard implementation uses separate input and output state vectors and computes each output entry from a small number of complex operations.
- Operational intensity below 1/2 makes the state-vector computation memory-bandwidth bound on most systems.
3.2 Single-core
The single-core kernels reduce memory and instruction inefficiencies through in-place computation, matrix and vector reordering, blocking, vectorization, and fused operations.
- In-place sparse matrix-vector multiplication halves memory requirements, but introduces a cache-unfriendly access pattern.
- 2^k-sized temporary vectors enable 2^(n-k) complex matrix-vector multiplications when applying a k-qubit gate to a 2^n state vector.
- Pre-permuting gate-matrix entries sorts qubit indices and makes memory accesses more local across repeated matrix-vector multiplications.
- Automatic code-generation and benchmarking feedback selects block sizes to keep the blocked computation’s temporary values in registers.
- Explicit vectorization parallelizes consecutive updates, theoretically providing 2x speedup with AVX or 4x with AVX512 for complex double precision.
- 2 fused multiply-accumulate instructions replace several multiplications, additions, and permutations after instruction reordering and matrix pre-computation.
3.3 Single-node
Single-node performance combines compute-intensity improvements from larger gates with cache-aware blocking and NUMA-aware OpenMP parallelization, evaluated on Edison and Cori II processors.
- Larger k-qubit gates increase operational intensity, while memory-bound gates can take nearly the same time despite performing more operations.
- The best gate size depends on peak performance, memory bandwidth, cache size and associativity, and the circuit being simulated.
- 2^k-way cache mapping can keep the 2^k state-vector values for each matrix-vector multiplication in distinct cache locations.
- OpenMP uses NUMA-aware initialization and loop collapsing to improve scaling beyond one NUMA node when outer loops have few iterations.
- Figure 2a and Figure 2b measure the combined optimizations on one Edison socket and one Cori II KNL socket, respectively.
3.4 Multi-node
Multi-node simulation distributes the state vector across MPI ranks and reduces communication by swapping global qubits into local positions before applying gates.
- More than 30 qubits require multiple nodes so the distributed state vector fits in memory.
- Local-qubit gates require no communication, whereas gates on global qubits require communication between ranks.
- The global-to-local scheme swaps global qubits with local ones, applies gates locally, and swaps them back when needed.
- For two ranks, a single-qubit swap exchanges state-vector blocks through an all-to-all operation.
- For four ranks, swapping two global qubits with two local qubits sends each rank’s state-vector quarter to the corresponding rank.
- Higher-level abstractions generalize global-to-local swaps to multiple or all global qubits while allowing optimized network-topology implementations.
3.5 Global gate specialization
Gate specialization identifies global gates that can be handled without communication, reducing the number of global-to-local swaps needed by quantum supremacy circuits.
- Controlled-NOT, controlled-Z, and T gates can avoid communication through rank renumbering, conditional phases or local operations, and absorbed global phases.
- 2x less communication is required for 36-qubit circuits because one global-to-local swap covers the entire depth-25 circuit.
- 42- and 45-qubit circuits require 2 global-to-local swaps with specialization, compared with 3 without gate specialization.
3.6 Circuit Optimizations: Gate scheduling and qubit mapping
Gate scheduling reduces communication and kernel overhead by grouping circuit operations into locally executable stages and merged clusters, while qubit mapping further improves execution efficiency.
- Gate scheduling: Gate scheduling is the most important circuit optimization because it reduces both multi-node communication and the number of k-qubit kernels used on a node.
- Gate scheduling: Stages reorder gates acting on different qubits so sequences can execute using local qubits, avoiding communication for operations that remain local.
- Qubit mapping: A 36-qubit supremacy circuit requires 1 rather than 2 global-to-local swaps after the mapping search, a 2x reduction.
- Gate scheduling: Clusters merge consecutive 1- or 2-qubit gates into k-qubit gates, greedily increasing k up to the performance limit kmax.
- Qubit mapping: Global-to-local swaps are also moved earlier when possible to remove undersized final clusters without increasing the total swap count.
- Qubit mapping: Bit remapping assigns frequently accessed qubits to low-order locations, and the heuristic produced a 2x decrease in time-to-solution.
4 IMPLEMENTATION AND RESULTS
The implementation combines optimized C++ kernels, Python-based scheduling, and MPI communication to simulate quantum supremacy circuits on Cori II and Edison. Results show strong node-level and multi-node performance, including a 45-qubit simulation using 8,192 KNL nodes and 0.5 PB of memory, while communication remains a major cost.
- Cori II results: 45 qubits were simulated using 8,192 Cori II KNL nodes and 0.5 PB of memory, achieving 0.428 PFLOPS averaged over the full simulation.Communication and synchronization accounted for 78% of the simulation time.
- Node-level performance: The 4-qubit Edison kernel scaled nearly perfectly across one 12-core socket, motivating two MPI processes per node for multi-node execution.The 5-qubit kernel scaled best to the full node but suffered a larger high-order-qubit performance drop than the 4-qubit kernel.
- Edison results: A single-socket 30-qubit simulation improved time-to-solution by 3x.This result was obtained on the Edison system.
- Edison results: The simulator achieved over 4x lower time-to-solution than the state-of-the-art baseline on an identical 64-socket Edison configuration.The comparison used a depth-25, 36-qubit circuit and therefore was not attributable solely to newer hardware.
- Edison results: The kernels averaged 47% of theoretical peak, or 218 GFLOPS per node, during the 36-qubit Edison simulation.Including communication, the full 64-socket simulation achieved 30% of peak performance, or 4.4 TFLOPS.
5 SUMMARY AND OUTLOOK
The work demonstrates large-scale quantum-circuit simulations and shows that further circuit-description optimization can substantially reduce communication requirements, although GPU support remains unfinished.
- 5 SUMMARY AND OUTLOOK: 45-qubit simulations were demonstrated using up to 8,192 nodes.Using the same compute resources, 46-qubit simulation is feasible with single-precision amplitudes.
- 5 SUMMARY AND OUTLOOK: The code generator improves performance portability across a wide range of processors, while extending it to GPUs remains ongoing.GPU support is identified as future work rather than a completed capability.
- 5 SUMMARY AND OUTLOOK: Circuit-description optimizations reduce required communication by an order of magnitude.For a 49-qubit quantum supremacy circuit, only two global-to-local swap operations would be required.
- 5 SUMMARY AND OUTLOOK: The low communication requirement may permit solid-state drives for simulations whose memory demands exceed current capabilities.The resulting simulation data may support verification and calibration of near-term quantum devices.