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Understanding Reduced-Voltage Operation in Modern DRAM Chips: Characterization, Analysis, and Mechanisms

Kevin K. Chang, Abdullah Giray Yağlıkçı, Saugata Ghose, Aditya Agrawal, Niladrish Chatterjee, Abhijith Kashyap, Donghyuk Lee, Mike O'Connor, Hasan Hassan, Onur Mutlu

arXiv:1705.10292v1cs.AR

TL;DR

DRAM energy is a significant system concern, motivating more aggressive voltage reduction than vendors conservatively provide. The paper characterizes reduced-voltage latency and reliability using real chips and circuit simulations, then proposes Voltron to reduce array voltage while controlling errors and performance loss.

  • Problem

    DRAM consumes a significant fraction of energy in modern computing systems, but aggressive voltage reduction requires understanding its effects on access latency and reliability.

  • Method

    The paper experimentally characterizes 124 DDR3L DRAM chips from three vendors, validates findings with circuit-level simulations, and proposes Voltron for performance-aware array voltage control.

  • Results

    The study finds that reduced voltage introduces bit errors when access latency is insufficient, while increasing activation, restoration, and precharge latency can eliminate them.

  • Takeaways & Limitations

    Voltron reduces DRAM energy without affecting memory data throughput by scaling only the DRAM array voltage and keeping peripheral circuitry at nominal voltage.

  • Takeaways & Limitations

    The experiments cannot precisely measure minimum activation and precharge latencies because the framework has 2.5ns latency granularity and voltage is continuous.

Abstract

from arXiv · show

The energy consumption of DRAM is a critical concern in modern computing systems. Improvements in manufacturing process technology have allowed DRAM vendors to lower the DRAM supply voltage conservatively, which reduces some of the DRAM energy consumption. We would like to reduce the DRAM supply voltage more aggressively, to further reduce energy. Aggressive supply voltage reduction requires a thorough understanding of the effect voltage scaling has on DRAM access latency and DRAM reliability. In this paper, we take a comprehensive approach to understanding and exploiting the latency and reliability characteristics of modern DRAM when the supply voltage is lowered below the nominal voltage level specified by DRAM standards. Using an FPGA-based testing platform, we perform an experimental study of 124 real DDR3L (low-voltage) DRAM chips manufactured recently by three major DRAM vendors. We find that reducing the supply voltage below a certain point introduces bit errors in the data, and we comprehensively characterize the behavior of these errors. We discover that these errors can be avoided by increasing the latency of three major DRAM operations (activation, restoration, and precharge). We perform detailed DRAM circuit simulations to validate and explain our experimental findings. We also characterize the various relationships between reduced supply voltage and error locations, stored data patterns, DRAM temperature, and data retention. Based on our observations, we propose a new DRAM energy reduction mechanism, called Voltron. The key idea of Voltron is to use a performance model to determine by how much we can reduce the supply voltage without introducing errors and without exceeding a user-specified threshold for performance loss. Voltron reduces the average system energy by 7.3% while limiting the average system performance loss to only 1.8%, for a variety of workloads.

1 INTRODUCTION

DRAM energy is a significant systems concern, motivating aggressive voltage reduction that preserves reliability and performance. The paper characterizes reduced-voltage behavior and proposes Voltron to trade array voltage, latency, energy, and performance loss.

  • DRAM consumes 40% of total energy in servers and 40% of total power in graphics cards.
  • The study examines how reduced supply voltage affects DRAM reliability, latency, and data retention using 124 chips from three major vendors.Experiments use 31 DIMMs containing the tested chips.
  • Below Vmin, bit errors emerge and increase exponentially as voltage drops further.Vmin is the minimum voltage at which no bit errors occur.
  • Increasing activation, restoration, and precharge latency prevents reduced-voltage errors because capacitor charge changes more slowly.Detailed circuit-level simulations validate and explain this behavior.
  • Voltage-induced errors cluster in physical chip regions, allowing longer operation latencies to be applied selectively where errors can occur.
  • Reduced supply voltage does not affect 64ms data-retention guarantees at 20℃ and 70℃ ambient temperature.
  • Voltron lowers only DRAM array voltage and uses a performance model to select voltage while respecting a user-specified performance-loss threshold.Its two components are array voltage scaling and performance-aware voltage control.
  • At 1.8% average performance loss, Voltron reduces DRAM energy by 10.5% and overall system energy by 7.3% across seven memory-intensive SPEC2006 workloads.The evaluation also reports energy savings on non-memory-intensive applications with very little performance impact.

2 BACKGROUND AND MOTIVATION

The paper introduces DRAM organization, access operations, timing, voltage domains, and prior voltage/frequency-scaling approaches. This background motivates reducing array voltage without lowering peripheral-circuit frequency or memory throughput.

  • 2.1 DRAM Organization: A DRAM module contains multiple chips controlled together, while each chip’s array contains banks organized into rows and columns.
  • 2.2 Accessing Data in DRAM: Reading one cache line requires ACTIVATE, READ, and PRECHARGE commands whose timing parameters are programmable by the memory controller.Activation latency is specified by tRCD.
  • 2.1 DRAM Organization: A DRAM chip contains a capacitor-based array and peripheral circuitry, with supply voltage distributed to both components.The array performs activation, restoration, and precharge operations under memory-controller timing.
  • 2.3 DRAM Power and Voltage: DDR3L uses a nominal supply voltage of 1.35V, with specified tolerance around that value.
  • 2.4 Memory Voltage and Frequency Scaling: Lowering DRAM frequency reduces transfer throughput and increases transfer time, making frequency scaling undesirable for bandwidth-demanding or latency-sensitive workloads.
  • 2.4 Memory Voltage and Frequency Scaling: The paper targets DRAM voltage reduction without sacrificing memory data throughput, based on comprehensive reduced-voltage characterization.

3 EXPERIMENTAL METHODOLOGY

The authors build an FPGA-based platform to control DRAM modules and test reduced-voltage behavior across a broad set of DDR3L chips and DIMMs. Tests vary voltage, access latencies, and data patterns while recording errors.

  • The SoftMC-based FPGA infrastructure provides precise control over DRAM modules for studying latency, reliability, and retention behavior.
  • The test corpus contains 31 DIMMs with 124 DDR3L chips from three major vendors.Each chip has 4Gb density and each DIMM has 2GB capacity; tests run at 800 MT/s.
  • Test 1 writes and reads every row in the DIMM at a specified supply voltage, activation latency, precharge latency, and data pattern.
  • The test writes a pattern and its inverse to adjacent rows, reads both rows, and records the resulting errors.

4 CHARACTERIZATION OF DRAM UNDER REDUCED VOLTAGE

Reducing DRAM supply voltage below a DIMM-specific threshold introduces errors, but increasing operation latency can restore reliable access. Errors vary across vendors and locations, and circuit simulations explain the voltage–latency relationship.

  • Below each DIMM’s Vmin, errors begin and the number of erroneous bits increases exponentially as voltage drops further.
  • Increasing activation, restoration, and precharge latency prevents voltage-induced errors because reduced voltage slows capacitor-charge changes.
  • At least 2.5ns additional tRCDmin and tRPmin is required for some DIMMs below Vmin, with vendor-dependent latency requirements.
  • At very low voltages, fewer DIMMs support error-free operation even with latencies up to 20ns; Vendor A DIMMs fail below 1.1V.
  • SPICE simulations fit Vendor B measurements and provide more precise reliable-latency estimates, while indicating that errors at very low voltage can occur during channel transfers.
  • Voltage-induced errors cluster in particular rows or banks, so only affected regions may require higher access latency.
  • Lower voltage increases data beats containing more than two errors, making SECDED ECC unlikely to alleviate these failures.

5 VOLTRON: REDUCING DRAM ENERGY WITHOUT SACRIFICING MEMORY THROUGHPUT

Voltron reduces DRAM energy by scaling array voltage while preserving channel frequency and compensating with latency increases. It selects voltage using application-specific performance modeling and memory-demand characteristics.

  • Voltron combines array voltage scaling with performance-aware control that automatically selects the minimum array voltage meeting a user-specified performance target.
  • Reducing only Varray preserves high channel frequency while lowering array power, but requires longer operation latency and can degrade performance.
  • Array voltage scaling reduces dynamic activate, precharge, and refresh power and part of static array power, with these components decreasing quadratically with array-voltage reduction.
  • Performance loss varies with application memory demand: it is piecewise linear with MPKI and increases with memory-stall fraction.
  • Voltron predicts performance loss from memory latency, MPKI, and memory-stall fraction using a piecewise linear OLS model.
  • At runtime, Voltron periodically selects the smallest available Varray whose predicted performance loss stays within the target.
  • The mechanism requires modest system changes, including power-delivery modifications because current DIMMs use a single supply voltage.

6 SYSTEM EVALUATION

The evaluation shows that Voltron reduces system energy across workload types while keeping performance loss generally small, with benefits especially pronounced for memory-intensive workloads. Its performance-aware and bank-locality-aware controls trade modest latency increases for energy efficiency, though the methodology derives restoration latency from simulation rather than experiments.

  • Methodology: Restoration latency under reduced voltage lacks experimental measurements and is instead derived from circuit simulations.The authors leave thorough experimental evaluation of tRAS under reduced-voltage operation to future work.
  • Performance-Aware Voltage Control: 2.5% average performance loss for non-memory-intensive workloads and 2.9% for memory-intensive workloads remain within Voltron’s 5% target.Voltron selects array voltages at runtime using its performance model; maximum losses are 4.4% and 4.1%, respectively.
  • Performance-Aware Voltage Control: 7.0% average system energy savings on memory-intensive workloads accompany 2.9% average performance loss, while MemDVFS has almost zero effect.Voltron remains within the specified 5% performance-loss target for these workloads.
  • System Energy Evaluation: 3.2% and 7.0% average system energy reductions occur for non-memory-intensive and memory-intensive workloads, respectively.The broader evaluation attributes the larger memory-intensive benefit to DRAM’s greater share of system energy in those workloads.
  • Spatial Locality of Errors: 7.3% average energy savings and 1.8% average performance loss result when Voltron exploits spatial locality by increasing latency only for affected banks.Voltron+BL improves over locality-unaware Voltron for memory-intensive workloads, reducing the latency penalty while preserving energy savings.
  • Heterogeneous Workloads: Heterogeneous workloads meet the 5% performance-loss target on average, but 10 of 50 workloads exceed it by 0.76% on average.Energy-efficiency improvement grows with workload memory intensity, whereas MemDVFS becomes less effective.

7 RELATED WORK

The paper distinguishes its reduced-voltage DRAM study from prior energy-efficiency techniques by experimentally characterizing real chips across voltage levels and targeting reliability, latency, and refresh behavior.

  • The study is presented as the first experimental characterization of modern low-power DRAM under reduced-voltage operation.
  • Prior DRAM voltage-scaling work does not comprehensively analyze reliability, latency, and refresh across a wide voltage range.
  • Unlike low-power modes, which have smaller effects on memory-intensive workloads, the paper reports that Voltron is especially effective for such workloads.
  • Voltron reduces DRAM array voltage while retaining nominal peripheral voltage, distinguishing it from techniques that reduce latency or improve parallelism.
  • The paper's reduced-voltage approach is orthogonal to SRAM-cache techniques, low-power standby modes, architectural power reductions, and refresh-reduction mechanisms.

8 CONCLUSION

The conclusion presents reduced-voltage DRAM as experimentally characterized and exploitable through latency-aware operation and Voltron's performance-constrained array-voltage scaling.

  • The study characterizes reduced-voltage DRAM behavior, including voltage effects on reliability, latency, error patterns, temperature, stored data, and retention.
  • Increasing activation, restoration, and precharge latency eliminates reduced-voltage bit errors and enables further voltage reduction without inducing data errors.
  • Voltron scales only the DRAM array voltage, keeps peripheral circuitry at nominal voltage, and uses a piecewise linear performance model to meet a performance-loss target.
  • The authors conclude that understanding voltage, reliability, and latency trade-offs can support mechanisms improving system performance, efficiency, or reliability.

A FPGA SCHEMATIC OF DRAM POWER PINS

Figure 20 shows the DRAM power pins controlled by the ML605 FPGA board.

  • The ML605 FPGA board controls the DRAM power pins.

B EFFECT OF DATA PATTERN ON ERROR RATE

The study examines BER across stored data patterns and supply voltages, finding that voltage reduction increases errors while pattern differences generally lack statistical significance.

  • The figure compares average BER for three hexadecimal fill patterns across supply-voltage levels, with error bars showing 95% confidence intervals.
  • BER increases as the supply voltage is reduced for all three tested data patterns.
  • Table 6 reports p-values for BER differences across patterns; p-values below 0.05 indicate statistically different BERs.
  • The three tested patterns—0xaa, 0xcc, and 0xff—do not generally produce significantly different BER values under reduced voltage.
  • Statistically significant pattern effects occur at 1.100V for Vendor A, 1.025V for Vendor B, and 1.250V and 1.100V for Vendor C.

C SPICE SIMULATION MODEL

The paper models a modern DRAM cell array in SPICE to simulate operation and access latency across reduced supply voltages.

  • Simulation Methodology: The simulations vary supply voltage to study DRAM cell-array behavior and access latency under reduced-voltage operation.
  • DRAM Cell Array Model: The simulated DRAM cell array uses a 512x512 organization, with each column sharing a bitline connected to a sense amplifier.Bitline parasitic resistance and capacitance arise from the wire and connected cells.
  • DRAM Cell Array Model: The model represents cells, bitlines, sense amplifiers, and their array-level electrical interactions.
  • Simulation Methodology: The methodology derives technology parameters from 55 nm DRAM and 45 nm process models, assuming 24 fF cell capacitance and 144 fF bitline capacitance.The nominal Varray is 1.35V.

D SPATIAL DISTRIBUTION OF ERRORS

Reduced-voltage errors are spatially nonuniform at higher voltage levels but become more numerous and widely distributed as voltage decreases further.

  • Spatial Distribution of Errors: At higher voltage levels, errors tend to cluster in particular DIMM regions even when errors occur.
  • Spatial Distribution of Errors: As supply voltage is reduced further, the number of errors increases and errors spread across the entire DIMM.
  • Spatial Distribution of Errors: Figures 23, 24, and 25 show physical error locations for representative DIMMs from Vendors A, B, and C.

E FULL INFORMATION OF EVERY TESTED DIMM

The appendix provides complete characteristics and experimentally determined error-free minimum voltages for the evaluated DDR3L DIMMs.

  • Full Information of Every Tested DIMM: Table 7 lists the parameters of every evaluated DRAM module together with its experimentally determined Vmin.Vmin is the minimum voltage level allowing error-free operation.
  • Full Information of Every Tested DIMM: The reported module characteristics include manufacturing date, timing factors, chip count, and marked DRAM die versions.Timing factors include frequency, tRCD, tRP, and tRAS.
  • Full Information of Every Tested DIMM: The evaluated modules are DDR3L DIMMs, and the testing platform supports DRAM modules up to 2GB.
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