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Error Characterization, Mitigation, and Recovery in Flash Memory Based Solid-State Drives

Yu Cai, Saugata Ghose, Erich F. Haratsch, Yixin Luo, Onur Mutlu

arXiv:1706.08642v3cs.AR

TL;DR

Scaling and multi-level coding increase NAND flash capacity and reduce cost, but make raw data reliability harder to ensure and can shorten SSD lifetime. The paper surveys the causes of these errors using real-device measurements, then reviews mitigation, correction, and recovery techniques. It concludes that increased raw error rates require increasingly sophisticated reliability mechanisms and motivates system-memory codesign for future scaling.

  • Problem

    NAND flash scaling and multi-level coding increase capacity and reduce cost but worsen raw-data reliability and can reduce SSD lifetime.

  • Method

    The paper surveys SSD reliability fundamentals, analyzes real state-of-the-art NAND devices experimentally, and reviews error mitigation, correction, and recovery techniques.

  • Results

    The survey finds that raw bit errors increase significantly as NAND flash scales, reducing SSD lifetime and requiring diverse mitigation and recovery mechanisms.

  • Takeaways & Limitations

    The paper provides practitioners with a foundation for understanding flash errors and their mitigation while informing future SSD and system-memory design.

  • Takeaways & Limitations

    3D NAND can have larger feature sizes than planar flash, so some planar-NAND error mechanisms are smaller or less significant in that setting.

Abstract

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NAND flash memory is ubiquitous in everyday life today because its capacity has continuously increased and cost has continuously decreased over decades. This positive growth is a result of two key trends: (1) effective process technology scaling, and (2) multi-level (e.g., MLC, TLC) cell data coding. Unfortunately, the reliability of raw data stored in flash memory has also continued to become more difficult to ensure, because these two trends lead to (1) fewer electrons in the flash memory cell (floating gate) to represent the data and (2) larger cell-to-cell interference and disturbance effects. Without mitigation, worsening reliability can reduce the lifetime of NAND flash memory. As a result, flash memory controllers in solid-state drives (SSDs) have become much more sophisticated: they incorporate many effective techniques to ensure the correct interpretation of noisy data stored in flash memory cells. In this article, we review recent advances in SSD error characterization, mitigation, and data recovery techniques for reliability and lifetime improvement. We provide rigorous experimental data from state-of-the-art MLC and TLC NAND flash devices on various types of flash memory errors, to motivate the need for such techniques. Based on the understanding developed by the experimental characterization, we describe several mitigation and recovery techniques, including (1) cell-to-cell interference mitigation, (2) optimal multi-level cell sensing, (3) error correction using state-of-the-art algorithms and methods, and (4) data recovery when error correction fails. We quantify the reliability improvement provided by each of these techniques. Looking forward, we briefly discuss how flash memory and these techniques could evolve into the future.

1 INTRODUCTION

SSDs achieve higher capacity and lower cost through process scaling and multi-level cell coding, but these same trends reduce NAND flash reliability. The paper reviews the resulting error mechanisms and the controller techniques used to characterize, mitigate, correct, and recover from errors.

  • Capacity and scaling: Process scaling increases the number of NAND flash cells within a fixed area, improving SSD capacity and cost-per-bit.NAND flash provides nonvolatile storage using floating-gate or charge-trap transistors; this paper mainly focuses on floating-gate transistors.
  • Capacity and scaling: Multi-level cell coding stores more than one bit per floating-gate transistor by dividing a fixed threshold-voltage range into multiple windows.Earlier SLC NAND used two voltage windows to represent one bit, whereas MLC NAND extends this approach to multiple bits per cell.
  • Reliability challenge: As stored charge decreases, process variation widens possible voltage distributions and shrinks margins between neighboring voltage windows, increasing raw bit errors.Error sources include cell wearout, programming errors, adjacent-cell interference, and charge leakage during data retention.
  • Reliability challenge: ECC detects and corrects raw bit errors, but stronger correction increases area overhead and latency, and data loss occurs when errors exceed ECC capacity.SSD lifetime is tied to the number of program/erase cycles completed without data loss while meeting a minimum retention guarantee.
  • Reliability challenge: Contemporary 1x-nm MLC SSDs sustain 3,000 P/E cycles, compared with 150,000 P/E cycles for older SLC SSDs.The comparison illustrates the reported reduction in endurance as raw flash reliability declines.
  • Paper scope: The paper combines SSD architecture, low-level NAND behavior, experimental error characterization, mitigation mechanisms, and data-recovery flows.It also discusses future effects of emerging flash and related memory technologies.

2 STATE-OF-THE-ART SSD ARCHITECTURE

A state-of-the-art SSD combines NAND flash chips with a controller that manages address translation, maintenance, error correction, and recovery. Its architecture exposes tradeoffs among correction strength, overprovisioning, write amplification, endurance, and reliability.

  • SSD architecture: An SSD connects a host interface to a controller, which communicates with multiple NAND flash chips through independent memory channels.The controller runs firmware, or the flash translation layer (FTL), and can use DRAM for metadata and cached pages.
  • Flash memory organization: NAND organization is hierarchical: chips contain dies, dies contain planes, and blocks contain sequentially numbered pages accessed at page granularity.Superblocks group blocks with matching IDs across chips and planes.
  • Controller functions: The FTL maps logical host addresses to physical flash locations and performs garbage collection, which remaps valid pages before erasing fragmented blocks.Wear leveling distributes P/E cycles across blocks to extend device lifetime.
  • Reliability mechanisms: Superpage-level parity can tolerate complete failure of one superpage data die during a logical-block access without data loss.Parity is generated by XORing corresponding data across planes and storing the result in a designated parity die.
  • Design tradeoffs: Increasing ECC strength reduces overprovisioning and increases write amplification, requiring manufacturers to balance correction capability against available spare space.For random-access workloads, increasing overprovisioning reduces write amplification, but the benefit shows diminishing returns.

3 NAND FLASH MEMORY BASICS

NAND flash stores data as threshold-voltage states in floating-gate cells organized into pages, blocks, and bitlines. Reading, programming, and erasing rely on reference voltages, pass-through operation, and Fowler–Nordheim tunneling.

  • 3.1 Storing Data in a Flash Cell: NAND flash stores data as charge-controlled threshold voltage in floating-gate transistors, whose insulated gates retain electrons without power.The floating gate is insulated by interpoly and tunnel oxide layers.
  • 3.1 Storing Data in a Flash Cell: MLC cells encode 2 bits across four states, while TLC cells encode 3 bits across eight threshold-voltage states.Each state occupies a voltage window, and programmed cells vary within that window.
  • 3.1 Storing Data in a Flash Cell: Figure 7 plots threshold voltage on the x-axis and probability density on the y-axis for the voltage distributions of MLC and TLC states.Each state appears as a probability-density curve spanning its voltage window.
  • 3.2 Flash Block Design: Flash blocks contain rows connected by wordlines, while cells in each column form bitlines connected to ground and a shared sense amplifier.Wordline cells form logical pages; bitline operations use GSL and SSL transistors.
  • 3.3 Read Operations: Reading decodes cell states with reference voltages: MLC LSB sensing uses one voltage, MSB sensing up to two, while TLC requires one, two, or four for LSB, CSB, and MSB.Unread cells receive pass-through voltage so the selected cell can be sensed on the shared bitline.
  • 3.4 Program and Erase Operations: Programming uses incremental step-pulse programming, repeatedly pulsing and verifying voltage until the target is reached, while two-step programming reduces MLC cell-to-cell interference.During concurrent wordline programming, cells reaching target voltage are inhibited from further pulses.

4 NAND FLASH ERROR CHARACTERIZATION

NAND flash errors accumulate through wearout, programming, interference, retention, and read disturb, with distinct mechanisms shaping threshold-voltage shifts and SSD failure rates. Experimental and large-scale studies reveal how these errors depend on cycling, device age, neighboring cells, retention time, read activity, and operating conditions.

  • Wearout and P/E Cycling: ~3,000 and ~1,000 P/E cycles per block are the endurance limits reported for 1x-nm MLC and TLC NAND flash, respectively.Blocks cycle through programming, reading, invalidation, and erasure until wearout prevents guaranteed data retention.
  • Wearout and P/E Cycling: As P/E cycles increase, tunnel-oxide degradation causes greater electron injection under fixed programming conditions, shifting threshold voltages higher and increasing program errors.Some cells intended for P1 or ER are instead programmed to the higher-voltage P2 or P3 states.
  • Program Errors: Program errors predominantly shift lower-voltage states upward, while scaled-down cells increase susceptibility to interference and read disturb during partial programming.TLC is less susceptible to these program errors than MLC because its SLC-buffer data has a lower error rate than partially programmed MLC wordline data.
  • Cell-to-Cell Program Interference: Wordline neighbors have the greatest coupling, and coupling coefficients grow as feature size decreases because smaller spacing increases effective capacitive interaction.For a fully programmed victim, the wordline immediately above is the major source of program interference because of NAND programming order.
  • Data Retention Errors: With increasing retention age, higher-voltage states shift lower, lower-voltage states shift higher, and every state distribution widens.TAT and SILC dominate leakage in high-voltage states, while hole loss contributes to upward shifts in the lowest-voltage states.
  • Read Disturb Errors: As read disturb operations increase, threshold voltages generally shift right, with lower-voltage states most affected and cells near the ER–P1 intersection especially vulnerable.The highest-voltage P7 state can instead decrease at its left tail because Vpass can move electrons from the floating gate to the control gate.
  • Large-Scale SSD Studies: SSD failure rates vary across reliability periods, rise with device age and temperature, exceed manufacturer specifications, and show as much as 81.7% variation between periods.Throttling can reduce the reliability impact of higher temperatures, while bad-block management helps keep uncorrectable errors lower than expected.

5 ERROR MITIGATION

The paper presents mitigation mechanisms that reduce NAND flash errors, adapt controller behavior to changing conditions, and extend SSD lifetime. These mechanisms address interference, retention, read disturb, voltage optimization, hot-data placement, and ECC overhead.

  • 5.1 Shadow Program Sequencing: Shadow program sequencing minimizes cell-to-cell interference on fully programmed wordlines and is used in commercial SSDs.It changes the order in which pages are written during two-step programming.
  • 5.2 Neighbor-Cell Assisted Error Correction: NAC extends NAND flash memory lifetime by 33% by reducing errors that consume limited ECC correction capability.NAC uses neighboring-cell information to assist error correction.
  • 5.3 Refresh Mechanisms: Adaptive refresh and read reclaim reduce retention and read disturb errors while limiting refresh-related overheads.Read reclaim remaps data to a new block after a block experiences many reads.
  • 5.5 Voltage Optimization: 64% endurance improvement and 10% lower error-correction latency result from sampling-based adaptive Vopt discovery.Because retention shifts threshold-voltage distributions leftward, read-retry can decrease reference voltages rather than search both directions.
  • 5.6 Hot Data Management: WARM improves average lifetime by 21% by separating write-hot data so recently overwritten blocks can skip refresh operations.Across workloads, almost 100% of writes target less than 1% of SSD pages, motivating hot-data management.

6 ERROR CORRECTION AND DATA RECOVERY TECHNIQUES

Modern SSDs use staged BCH or LDPC error correction, followed by parity recovery when decoding fails. Soft LDPC decoding improves correction strength by accumulating information from additional reads, but increases latency and relies on approximate LLR models.

  • Error correction flow: SSD error correction proceeds from hard BCH/LDPC decoding to soft LDPC decoding and finally superpage-level parity recovery when earlier stages fail.The flow uses initial reads and ECC decoding, then escalates to more expensive techniques when errors remain uncorrectable.
  • LDPC soft decoding: Each additional soft-decoding level adds optimized read-reference voltages and new cell information, strengthening LDPC correction beyond hard decoding.Cells are binned into threshold-voltage ranges, and manufacturer-provided LLR values are supplied to the decoder.
  • LLR estimation: AWGN-based LLRs are estimates because NAND threshold distributions are non-Gaussian, range means approximate cells, and state variances differ.Proposed improvements include transformations, scaling, ECC-guided optimization, and empirical training.
  • Error correction strength: At target UBER 10^-16, BCH with coding rate 0.935 corrects RBER 1.0 × 10^-3, whereas soft LDPC with rate 0.936 reaches 5.0 × 10^-3.Soft LDPC tolerates up to five times the raw bit errors as BCH, at the cost of additional read operations.
  • Error correction strength: With 0.28% more reads, combined hard and soft LDPC decoding provides twice the error correction strength of BCH codes.The estimate assumes 0.01% of codeword corrections fail and seven additional reads are required for soft LDPC.
  • Reliability margin: The LDPC reliability margin allows SSD lifetime to be traded against read latency because acceptable UBER can persist beyond the example’s capped lifetime RBER.In the example, soft LDPC maintains UBER 10^-16 up to RBER 5.0 × 10^-3, despite the lifetime cap at 2.0 × 10^-3.
  • Data recovery: RFR and RDR reduce the raw bit error rate of failed pages by 50% and 36%, respectively.These recovery mechanisms target pages that remain problematic after ordinary correction.

7 EMERGING RELIABILITY ISSUES FOR 3D NAND FLASH

3D NAND increases density through vertically stacked layers and currently larger feature sizes, which can reduce some planar-NAND reliability issues. However, retention errors may worsen, and rigorous studies of 3D NAND error characteristics and mitigation remain unpublished.

  • 3D NAND vertically stacks multiple layers and commonly uses charge trap transistors to increase density and scalability.
  • Larger feature sizes in current 3D NAND reduce read disturb and cell-to-cell program interference compared with small-feature planar NAND.These devices can revert to one-shot programming because program interference is less significant at larger process technologies.
  • 3D NAND endurance has increased by over an order of magnitude as larger transistors permit higher maximum P/E cycle counts.
  • Rigorous studies of 3D NAND error characteristics and mitigation techniques have yet to be published.
  • Retention errors are likely to become exacerbated in 3D NAND, while the relative benefits of the described mitigation techniques remain unevaluated.The techniques are expected to remain applicable, but their benefits have yet to be measured for 3D NAND.

8 SIMILAR ERRORS IN OTHER MEMORY TECHNOLOGIES

DRAM and emerging memories share several reliability concerns with NAND flash, including retention, interference, and read-disturb errors. The section connects these mechanisms to ECC tradeoffs, specialized mitigation opportunities, and practical security vulnerabilities such as RowHammer.

  • DRAM shares NAND flash’s major error sources: data retention, cell-to-cell interference, and read disturb.
  • DRAM retention errors arise from charge leakage in capacitors and can cause data loss much faster than leakage in NAND flash cells.
  • DRAM mitigation techniques reduce refresh frequency or reduce refresh interference with demand requests.
  • Data pattern dependence makes DRAM retention time depend on values written to nearby cells, illustrating cell-to-cell interference.
  • Repeatedly accessing a DRAM row can flip bits in adjacent rows, producing read-disturb errors known as RowHammer-induced errors.
  • RowHammer can let user-level software induce errors and compromise systems, including gaining kernel-level privileges or taking over servers and virtual machines.
  • DRAM ECC is weaker than SSD ECC because DRAM prioritizes low latency, has lower error rates, and uses smaller access granularity.
  • As DRAM scales, increasing error rates motivate ECC in all modules, more efficient ECC, and error-specific mitigation mechanisms.

9 CONCLUSION

The paper surveys NAND-flash SSD reliability, characterizes error mechanisms with real-chip data, and reviews mitigation and recovery techniques. It concludes that these techniques can offset some lifetime losses from scaling and motivates system-memory codesign for future platforms.

  • The paper surveys fundamentals and recent research on NAND-flash-memory-based SSD reliability.
  • Scaling increases raw bit-error rates and reduces SSD lifetime, while mitigation and recovery techniques undo some of those lifetime reductions.
  • The survey focuses on MLC and TLC NAND using real-chip data and argues that the techniques should also apply to emerging 3D NAND.
  • The paper advocates system-level codesign of systems and memory to enhance the scaling of future computing platforms.

APPENDIX: TLC THRESHOLD VOLTAGE DISTRIBUTION DATA

The appendix provides normalized threshold-voltage distribution statistics for TLC NAND states across P/E cycle counts, retention times, and read-disturb counts.

  • Table 4 reports normalized means and standard deviations for each TLC voltage state at various P/E cycle counts.
  • Table 5 reports normalized means and standard deviations for each TLC voltage state at various data retention times.
  • Table 6 reports normalized means and standard deviations for each TLC voltage state at various read-disturb counts.

ABOUT THE AUTHORS

The authors bring expertise spanning solid-state drive architecture, flash and DRAM reliability, computer architecture, and systems research, alongside substantial industry experience and professional recognition.

  • Yu Cai has worked as a solid-state disk system architect at SK Hynix, Seagate Technology, Avago Technologies, and LSI Corporation.
  • The authors have received best-paper and runner-up awards from HPCA and DFRWS, while Haratsch holds more than 100 U.S. patents.
  • Erich F. Haratsch directs flash-controller architecture at Seagate Technology, focusing on SSD performance, quality of service, endurance, error correction, and media management.
  • Yixin Luo researches DRAM and flash reliability as well as datacenter reliability and cost optimization at Carnegie Mellon University.
  • Onur Mutlu is a professor at ETH Zürich and a Carnegie Mellon faculty member whose broader interests include computer architecture, systems, and bioinformatics.
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