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Encoding Neural and Synaptic Functionalities in Electron Spin: A Pathway to Efficient Neuromorphic Computing

Abhronil Sengupta, Kaushik Roy

arXiv:1711.02235v4cs.ET

TL;DR

Neuromorphic computing seeks brain-like efficiency, while IoT applications may require on-chip learning from unlabeled real-time data. This review connects spintronic device physics to neural and synaptic functions and reports simulated All-Spin advantages over CMOS.

  • Problem

    IoT intelligence often needs on-chip learning from unlabeled real-time data, while backpropagation requires labeled inputs and supervised training.

    Source: III.2. Spike-Timing Dependent Plasticity · p. 8

  • Method

    The review connects spin-transfer-torque device physics and experimental results to spintronic neural and synaptic structures across device, circuit, system, and algorithm levels.

    Source: §I · p. 2

  • Results

    MNIST simulations report 250× energy and 56× EDP improvement over 45nm CMOS; system-level comparisons report 204–2759× energy improvement and 3–665× speedup.

    Source: §V.1 · p. 20, §V.3 · p. 21

  • Takeaways & Limitations

    Spintronic devices offer potential for energy-efficient, nonvolatile in-memory neuromorphic computing and on-chip learning.

    Source: §I · p. 2, III.2. Spike-Timing Dependent Plasticity · p. 8

    Experimental demonstration of full network-level synaptic learning and neural inference using spintronic devices remains unexplored.

    Source: §VI · p. 22

Abstract

from arXiv · show

Present day computers expend orders of magnitude more computational resources to perform various cognitive and perception related tasks that humans routinely perform everyday. This has recently resulted in a seismic shift in the field of computation where research efforts are being directed to develop a neurocomputer that attempts to mimic the human brain by nanoelectronic components and thereby harness its efficiency in recognition problems. Bridging the gap between neuroscience and nanoelectronics, this paper attempts to provide a review of the recent developments in the field of spintronic device based neuromorphic computing. Description of various spin-transfer torque mechanisms that can be potentially utilized for realizing device structures mimicking neural and synaptic functionalities is provided. A cross-layer perspective extending from the device to the circuit and system level is presented to envision the design of an All-Spin neuromorphic processor enabled with on-chip learning functionalities. Device-circuit-algorithm co-simulation framework calibrated to experimental results suggest that such All-Spin neuromorphic systems can potentially achieve almost two orders of magnitude energy improvement in comparison to state-of-the-art CMOS implementations.

I. INTRODUCTION

Neuromorphic computing seeks to address the mismatch between brain-like processing and conventional CMOS by exploring spintronic devices that can implement neural and synaptic functions. The paper reviews a cross-layer path from spin-device physics to neuromorphic systems.

I. INTRODUCTION

  • CMOS neuromorphic architectures retain von Neumann logic and memory, while their hardware mismatch with brain-like processing contributes to much higher resource and power use.The cited comparison describes CMOS neuromorphic resource and power use as orders of magnitude higher than the biological brain.Source: §I · pp. 1–2
  • Spintronic devices may combine diverse neural and synaptic functions in a single low-voltage device structure, motivating a cross-layer review of their potential.The review links device physics and experiments to device, circuit, system, and algorithm design.Source: §I · p. 2

II. SPINTRONIC DEVICES: UNDERLYING PHYSICAL PHENOMENA

  • Spin-transfer torque manipulates magnetization, while tunneling magnetoresistance reads its state in magnetic tunnel junctions.The paper frames these as the principal “write” and “read” mechanisms for neuromimetic spin devices.Source: §II · p. 2, II.1. Device Fundamentals · p. 3

II.1. Device Fundamentals

  • A nanomagnet has two opposite stable magnetization directions, with its thermal stability set by an anisotropy-dependent energy barrier.In the absence of external perturbation, magnetization relaxes to either stable direction; the barrier height depends on uniaxial anisotropy and magnet volume.Source: II.1. Device Fundamentals · p. 2
  • In a magnetic tunnel junction, parallel free- and pinned-layer magnetizations yield lower resistance than antiparallel alignment, enabling resistance-based state sensing.Spin-transfer torque can switch the free layer between these configurations, with switching direction depending on current direction.Source: II.1. Device Fundamentals · p. 3

II.2. Domain Wall Motion

Domain walls let elongated magnets represent more than two states, with the wall position encoding the relative proportions of oppositely polarized domains.

II.2. Domain Wall Motion

  • A domain wall between oppositely polarized regions enables more than two magnetic states, represented by the wall position or relative domain proportions.Uniformly magnetized single-domain magnets represent only two binary states.Source: II.2. Domain Wall Motion · pp. 3–4
  • Domain-wall type depends on anisotropy and strip geometry: PMA nanostrips exhibit Néel walls when narrow and Bloch walls when wider.In-plane-anisotropy nanowires instead exhibit transverse or vortex walls depending on strip dimensions.Source: II.2. Domain Wall Motion · p. 4, Figure 2 · p. 4
  • Charge-current-induced domain-wall motion proceeds in the direction of electron flow and is attributed to spin torque from electrons tracking local magnetization.Source: II.2. Domain Wall Motion · p. 4

II.3. Spin-Orbit Torque

Spin-orbit torque uses charge current through a heavy-metal layer to inject spin into an adjacent ferromagnet, offering an alternative to spin-transfer-torque injection.

II.3. Spin-Orbit Torque

  • The spin-Hall effect in a heavy metal converts charge-current flow into spin current at the adjacent ferromagnet interface.The injected spin polarization is orthogonal to both the charge-current and spin-current directions described in the paper.Source: II.3. Spin-Orbit Torque · p. 4
  • When the ferromagnet width greatly exceeds the heavy-metal thickness, spin injection efficiency can exceed 100%, with spin current larger than charge current.The spin-current-to-charge-current conversion is proportional to the spin-Hall angle.Source: II.3. Spin-Orbit Torque · p. 4
  • Spin-orbit-torque reversal directly suits in-plane-anisotropy magnets, whereas perpendicular-anisotropy magnets require an external magnetic field for switching.Source: II.3. Spin-Orbit Torque · p. 5
  • In PMA multilayers with spin-orbit coupling and broken inversion symmetry, DMI stabilizes fixed-chirality Néel walls that injected spins can displace.Bloch-wall motion in PMA multilayers with negligible DMI has also been achieved in an external magnetic field.Source: II.3. Spin-Orbit Torque · p. 5

II.4. Lateral Spin Valves

Lateral spin valves inject spin through a nonmagnetic channel, while device-efficiency improvements and neuromorphic computation place these mechanisms in a broader design context.

II.4. Lateral Spin Valves

  • In a lateral spin valve, spin accumulation beneath an injector drives non-local torque on a detector, while injected spin current decays exponentially with injector-detector distance.Longer spin-flip-length materials or a tunnel barrier can improve spin injection.Source: II.4. Lateral Spin Valves · p. 5

II.5. Towards More Efficient Devices

  • Higher TMR is important for synapses because increased resistance contrast can improve distinguishability when scaling neuron inputs.Theoretical AP/P resistance ratios approach 300, experiments reached 600% variation, and an IEEE roadmap predicted 1000% within ten years.Source: II.5. Towards More Efficient Devices · p. 5

III. NEUROMORPHIC COMPUTATION: PRELIMINARIES

  • Neuromorphic computation uses plastic synapses to modulate transmitted signals, with pattern recognition relying on synaptic plasticity in response to neural signals.Source: §III · p. 5
  • A crossbar maps inputs and synaptic weights to parallel dot products, whereas CMOS architectures store weights in SRAM and incur memory-transfer and leakage energy.Source: Figure 3 · p. 6

III.1. Neural Computation

Neuromorphic networks map weighted inputs to neural units, with crossbars performing parallel weighted sums in memory. Spiking models add event-driven learning and computation, while stochastic neurons and homeostasis capture additional neural behaviors.

III.1. Neural Computation

  • Crossbar arrays perform parallel input–weight dot products in memory, while digital CMOS systems fetch synaptic weights from SRAM and are limited by memory access and leakage energy.Memory access and leakage typically account for ~60–80% of total energy in pattern-recognition workloads.Source: III.1. Neural Computation · p. 6
  • Neurons progress from binary step outputs to analog non-step outputs and time-series spikes, with analog outputs supporting greater information encoding.Non-step transfer-function gradients also supply information used by backpropagation.Source: III.1. Neural Computation · pp. 6–7
  • Spiking neurons encode inputs as time-series events; LIF neurons integrate weighted spikes and reset when membrane potential crosses a threshold.Inputs can use Poisson rate encoding, where spike frequency over a time window is proportional to input value; LIF models also include a refractory period.Source: III.1. Neural Computation · p. 7
  • Spiking networks support on-chip STDP learning and can exploit sparse, event-driven operation, though temporal encoding increases inference delay.Spike inputs can replace synaptic multiplications with multiplexing, and weights need only be fetched upon an input event.Source: III.1. Neural Computation · p. 7
  • Deterministic converted spiking models do not capture probabilistic neural computation, motivating stochastic neurons whose response probability varies with input.Spintronic devices are of interest because time-varying thermal noise gives them stochastic behavior.Source: III.1. Neural Computation · pp. 7–8
  • Homeostasis raises a neuron's threshold after each spike, making repeated dominance in a neuron pool progressively harder.This spike-frequency adaptation mechanism is used in SNN pattern-recognition systems.Source: III.1. Neural Computation · p. 8

III.2. Spike-Timing Dependent Plasticity

STDP offers a local, unsupervised alternative to backpropagation for synaptic learning in spiking networks. The rule updates weight according to pre- and post-neuron spike timing, while probabilistic single-bit variants address limited synaptic bit resolution.

III.2. Spike-Timing Dependent Plasticity

  • Backpropagation requires supervised labels and a backward gradient pass through the network, making specialized on-chip hardware costly in power and area.On-chip learning is especially relevant where IoT devices need embedded intelligence and incoming data are unlabeled.Source: III.2. Spike-Timing Dependent Plasticity · p. 8
  • STDP potentiates a synapse when the pre-neuron spikes before the post-neuron and depresses it when the order is reversed, with change decaying exponentially with timing difference.The rule is based on measurements from rat hippocampal glutamatergic synapses.Source: III.2. Spike-Timing Dependent Plasticity · p. 8, Figure 4 · p. 9
  • STDP is unsupervised and local because weight updates depend only on the activities of connected neurons, enabling lower-cost on-chip learning.Recognition accuracies based on STDP were still described as preliminary, although competitive accuracies had been achieved in digit recognition and sparse encoding.Source: III.2. Spike-Timing Dependent Plasticity · p. 8
  • Probabilistic single-bit STDP replaces multi-bit weight updates with binary state changes, matching stochastic switching behavior in nanoscale synapses.Competitive digit-recognition accuracy with stochastic single-bit learning had been demonstrated in SNNs.Source: III.2. Spike-Timing Dependent Plasticity · p. 8

III.3. Volatile Synaptic Learning

Volatile synaptic learning models transient changes that can stabilize under frequent stimulation, while network connectivity choices shape scalability and pattern recognition. CNNs use local, shared kernels; STDP networks use excitatory inputs, inhibition, and homeostasis.

III.3. Volatile Synaptic Learning

  • Frequent action potentials can move synapses from transient STP to stable LTP, whereas infrequent inputs allow the volatile change to decay.STP-LTP is described as frequency-dependent volatile learning, unlike non-volatile STDP, and may support adaptive unlearning as environments change.Source: III.3. Volatile Synaptic Learning · p. 9
  • The STP-LTP model is often analogized to STM and LTM: information transfers from limited-duration storage to longer-term storage when input is repeated sufficiently.The same psychological concepts have also been used to model computational units in RNN architectures.Source: III.3. Volatile Synaptic Learning · p. 9

III.4. Network Connectivity

  • Fully connected networks scale poorly because they lack translation and scaling invariance and require many weights and connections.CNNs address these challenges through convolutional connectivity inspired by local receptive fields and feature sensitivity in the visual cortex.Source: III.4. Network Connectivity · pp. 9–10
  • CNNs cascade convolution and subsampling layers, then typically use fully connected output layers; local fan-in and shared kernels reduce learned weights and training time.Convolution also provides resilience to image translation and scaling.Source: III.4. Network Connectivity · p. 10, Figure 5 · p. 10
  • A common STDP network uses all-to-all excitatory inputs, lateral inhibition, and homeostasis to help neurons respond selectively to input patterns.Training deeper networks using STDP remains an active research area.Source: III.4. Network Connectivity · p. 10, Figure 5 · p. 10
  • RNN neurons receive their prior time-step output alongside external input, enabling context learning in sequential tasks without changing the core neuron or synapse functions.The same neural and synaptic spin devices can therefore be used in these different algorithmic architectures.Source: III.4. Network Connectivity · p. 10

IV. SPINTRONIC DEVICE PROPOSALS AND CORRESPONDENCE TO NEURAL AND SYNAPTIC FUNCTIONALITIES

The paper reviews spintronic devices that map spin-torque behavior to neural and synaptic functions. For step neurons, presetting a PMA magnet along an unstable axis lowers switching-current requirements; a reported CoFeB device consumed ~15 fJ, about a 3× energy improvement over corresponding CMOS.

IV. SPINTRONIC DEVICE PROPOSALS AND CORRESPONDENCE TO NEURAL AND SYNAPTIC FUNCTIONALITIES

Step Neurons

  • A conventional MTJ step neuron uses switching between parallel and antiparallel states to implement a threshold response, but high bias and reset currents limited energy improvement to ~1.63× over digital CMOS.The implementation mapped the MTJ switching event to neuron function without considering internal time-domain magnetization dynamics.Source: Step Neurons · p. 11
  • Presetting a PMA magnet along its unstable hard axis lets a small input synaptic current select either stable state, reducing the critical switching-current requirement.The proposal uses separate Preset and Evaluation stages, with the input current determining the final state during the magnet's relaxation time.Source: Step Neurons · p. 11
  • The neuron operation involved ∼15 fJ energy consumption, yielding ∼3× improvement in energy consumption over a corresponding CMOS neuron, with magnetic parameters based on measurements reported in Ref.106.The magnet measured 4 × 40 × 40 × 1.5 nm3 and used a β-W underlayer.Source: Step Neurons · p. 11
  • An LSV step-neuron design uses excitatory, inhibitory, and preset magnets, but spin-flip decay in the channel constrains fan-in and an MgO tunneling barrier increases energy use.Channel materials for efficient spin-current injection were under exploration.Source: Step Neurons · pp. 12–13

Non-Step Neurons

Domain-wall motion enables multilevel neuronal states, while single-domain MTJs support spiking behavior through their magnetization dynamics. The section describes deterministic and stochastic neuron operation, including low-energy switching.

Non-Step Neurons

  • 15–20 intermediate resistive states were reported for a DW-motion device, whereas a mono-domain MTJ represents only two neuron outputs.A multi-domain free layer can provide multiple resistive states through domain-wall position.Source: Non-Step Neurons · p. 13
  • A DW-motion neuron integrates input current into wall displacement, reads its position through a resistive divider, and resets by reversing current.For an 80nm × 20nm free layer, simulations show 10.6µA can move the wall edge-to-edge in 2ns, with 0.1fJ total write and reset energy.Source: Non-Step Neurons · p. 13

Spiking Neurons

  • An IF spiking neuron fires when the domain wall reaches the free-layer edge, with reverse current providing leak.In a single-domain MTJ, magnetization acts like membrane potential: input spin current integrates toward switching, while the magnetization leaks back if the pulse ends early.Source: Spiking Neurons · pp. 13–14
  • Thermal noise makes MTJ spiking stochastic, requiring successive write, read, and reset cycles to determine and restore neuron state.The read stage determines MTJ resistance; the device is reset when a spike is generated.Source: Spiking Neurons · p. 14
  • ∼1 fJ is the average energy for a 0.5-ns write cycle switching a CoFe(1.2nm)-W(2nm) MTJ with probability 0.5.The evaluated elliptic IMA magnet measures π/4 × 100 × 40nm2 and requires ∼71µA input current.Source: Spiking Neurons · p. 14

Emergent Neural Behavior: Bursting, Oscillations, Stochastic Resonance

The section surveys spintronic approaches to emergent neural behaviors and describes domain-wall-based STDP. It connects device behavior and circuit choices to timing-dependent plasticity and synaptic energy considerations.

Emergent Neural Behavior: Bursting, Oscillations, Stochastic Resonance

  • MTJ back-hopping between stable and unstable states is interpreted as resembling biological spike bursting [103].Networks of spin-torque oscillators can model synchronized oscillations through locking mechanisms [117,118]; synchronization of nine spin-Hall nano-oscillators was demonstrated experimentally [119].Source: Emergent Neural Behavior: Bursting,… · p. 14
  • Spin-torque devices’ thresholding and stochasticity can be used for stochastic resonance, where an optimum noise level improves signal-to-noise ratio [121].Spintronic oscillator platforms have also been demonstrated for neuromorphic computing [120].Source: Emergent Neural Behavior: Bursting,… · p. 14

Spike-Timing Dependent Plasticity

  • In DW synapses, programming current scales with wall displacement and conductance change, while decoupled read and write paths keep programming current independent of present MTJ conductance.This provides a device basis for timing-dependent conductance updates; the device conductance varies with domain-wall position.Source: Spike-Timing Dependent Plasticity · p. 15
  • Subthreshold-saturation biasing of the programming transistor produces exponential current dynamics for STDP, provided current stays approximately constant during each programming interval.The cited timing constants are ∼µs and the POST duration is 1ns; the described gate voltage rises linearly from 0.2 to 0.6V with drain voltage at 0.6V.Source: Spike-Timing Dependent Plasticity · p. 15, Figure 7 · p. 16
  • Operating synapses below 100mV preserves greater separation between maximum and minimum conductance states, which is desirable for pattern-recognition accuracy.Higher applied voltage reduces the achievable synaptic conductance ratio, particularly because AP-state resistance depends more strongly on voltage.Source: Spike-Timing Dependent Plasticity · p. 16
  • Spin-orbit-torque CoFe-Pt synapses were predicted to use an order of magnitude less programming energy per event than a 4-bit SRAM synapse at 10nm [125].The discussion contrasts this with analysis reporting twice the power for analog neuromorphic systems based on typical emerging memristive technologies versus digital counterparts [125].Source: Spike-Timing Dependent Plasticity · p. 17

Probabilistic Synaptic Learning

Probabilistic STDP uses stochastic switching in mono-domain MTJs to vary synaptic update probability with spike timing. Low switching probability supports non-greedy learning and reduces operating requirements.

Probabilistic Synaptic Learning

  • Update probability is typically kept below 0.1 for non-greedy learning, reducing device operating current and voltage requirements.Crossbar architectures have been proposed with update probability varying exponentially with spike timing [7].Source: Probabilistic Synaptic Learning · p. 17
  • A prior simplified probabilistic STDP implementation used constant state-change probability in both positive and negative timing windows [91].The timing-varying update approach is described in contrast to this simplified rule.Source: Probabilistic Synaptic Learning · p. 17
  • In mono-domain MTJ synapses, sigmoidal stochastic switching and saturation-biased MSTDP can implement probabilistic STDP with write current decreasing linearly as spike timing increases.The linear current variation emulates exponential probabilistic STDP characteristics in the low switching-probability regime.Source: Figure 8 · p. 17, Probabilistic Synaptic Learning · p. 17

IV.3. Volatile Synaptic Learning

Mono-domain MTJs can model frequency-dependent volatile synaptic learning through leaky magnetization dynamics. More frequent stimuli increase switching likelihood, distinguishing short- and long-term plasticity.

IV.3. Volatile Synaptic Learning

  • Five 1-ns current pulses spaced 3ns apart switch the MTJ to the opposite state (LTP), whereas 6ns spacing leaves it unable to switch (STP).The different responses arise from leaky-integrate magnetization dynamics: magnetization begins switching under a pulse but leaks back when the pulse ends before switching completes.Source: IV.3. Volatile Synaptic Learning · p. 17, Figure 9 · p. 18
  • Frequency-dependent volatile learning requires a device with two stable resistive states and metastable transitions in response to stimuli.The mono-domain MTJ is proposed as a device matching this behavior.Source: IV.3. Volatile Synaptic Learning · p. 17
  • MTJ paired-pulse facilitation and post-tetanic potentiation measurements closely resemble those at frog neuromuscular junctions [128,129].Paired-pulse facilitation is an increase in plasticity when a second similar stimulus follows; post-tetanic potentiation is progressive plasticity increase after successive stimuli.Source: IV.3. Volatile Synaptic Learning · p. 18

V.1. All-Spin Neural Networks

All-Spin neural networks map weighted inputs onto spintronic crossbars for parallel dot-product computation and neuron processing. Simulations report substantial energy improvements over CMOS for deterministic and stochastic MNIST networks.

V.1. All-Spin Neural Networks

  • A crossbar stores synaptic weights as conductances and sums weighted input currents along columns to supply each neuron's dot-product input.Spiking inputs apply high voltage to their rows; non-spiking inputs apply low voltage. Figure 10(a) depicts the mapping.Source: §V.1 · p. 18, Figure 10 · p. 19
  • Spintronic neurons' low write resistance and decoupled read/write paths support low-voltage crossbar operation without routing synaptic input current through the MTJ oxide.These properties also allow spintronic devices to serve as both neuronal and synaptic units.Source: §V.1 · pp. 18–19
  • Bipolar weights use paired input rows driven at +∆V and −∆V for spikes, with conductances programmed according to weight sign.The non-ideality parameter γ can be kept small by adjusting write-cycle duration, although shorter cycles increase stochastic switching dispersion.Source: §V.1 · p. 19
  • 250× improvement in energy consumption and 56× improvement in EDP were reported for an All-Spin SNN on MNIST versus baseline digital CMOS.The 45nm comparison optimized the write cycle to 2ns and achieved approximately 98.5% test accuracy.Source: §V.1 · p. 20
  • Stochastic sigmoid neurons approximate offline-trained sigmoid networks, but longer write cycles steepen switching characteristics and increase sensitivity to process and temperature variations.The transfer functions are not exactly equivalent, though the cited work reports they can achieve similar recognition accuracy.Source: §V.1 · p. 20
  • 20× greater energy efficiency than baseline CMOS was estimated for an MTJ-enabled stochastic SNN using a 0.5ns write cycle and 50 time-steps per image.The network was evaluated on MNIST for competitive classification accuracy.Source: §V.1 · p. 20

V.2. STDP Learning

The section describes STDP crossbar learning and system-level benchmarking of All-Spin SNNs. Co-simulation reports energy and speed improvements over CMOS, while the outlook notes that full network-level experimental demonstrations remain unexplored.

V.2. STDP Learning

  • Probabilistic spintronic STDP networks achieved approximately 80% MNIST training-set recognition accuracy with 225 excitatory neurons, with competitive accuracy reported above 1000 neurons.The crossbar connects pre-neuron spike rows to post-neurons, and synapses are programmed following post-neuron spikes.Source: §V.2 · p. 20
  • Telegraphic switching in low-barrier magnets requires circuit considerations for these learning networks.The system-level benchmark architecture uses 32 × 32 crossbars time-multiplexed with global control logic.Source: §V.2 · p. 21, §V.3 · p. 21
  • LT-ST crossbar arrays reduced total training programming energy by approximately 2× versus a single crossbar in an isoaccuracy analysis, with minimal area penalty.The LT array learns strongly time-correlated representations; the ST array acquires moderately correlated general features.Source: §V.2 · p. 21

V.3. System Level Benchmarking

  • 204−2759× improvement in energy consumption and 3−665× performance speedup were projected against the CMOS baseline by hybrid co-simulation.The system-level results use a predictive framework with device models calibrated to experimental measurements; Figure 11 compares energy and speed across six recognition applications.Source: §V.3 · p. 21, Figure 11 · p. 21

VI. OUTLOOK

  • Full network-level experimental demonstrations of spintronic synaptic learning and neural inference remain unexplored, and device- and algorithm-level innovations are still needed.The article characterizes the field as evolving, with preliminary experiments providing proof-of-concept for proposals.Source: §VI · p. 22
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