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A Crossbar Network for Silicon Quantum Dot Qubits
R. Li, L. Petit, D. P. Franke, J. P. Dehollain, J. Helsen, M. Steudtner, N. K. Thomas, Z. R. Yoscovits, K. J. Singh, S. Wehner, L. M. K. Vandersypen, J. S. Clarke, M. Veldhorst
TL;DR
Scaling quantum-dot spin qubits from single- and few-qubit demonstrations to practical computation requires architectures that address interconnect and connectivity challenges. This paper proposes a shared-control crossbar architecture and reports high-fidelity, frequency-selective single-qubit operations while supporting shuttling and long-range coupling prospects.
Problem
Scaling qubit numbers for practical computations remains a central challenge, while larger quantum simulations face connectivity problems across devices.
Method
The paper proposes a two-dimensional quantum-dot crossbar using shared control, scalable lines, independently controlled detuning and tunneling, and electron shuttling for selective operations.
Results
Single-qubit fidelities above 99.9% with crosstalk below 0.1% are achieved using GRAPE pulses, with π/2 rotations completed within 250 ns.
Takeaways & Limitations
Shuttling and flexible connectivity provide prospects for long-range entanglement, topological error-correction codes, and large-scale quantum computation.
Abstract
from arXiv · showhide
The spin states of single electrons in gate-defined quantum dots satisfy crucial requirements for a practical quantum computer. These include extremely long coherence times, high-fidelity quantum operation, and the ability to shuttle electrons as a mechanism for on-chip flying qubits. In order to increase the number of qubits to the thousands or millions of qubits needed for practical quantum information we present an architecture based on shared control and a scalable number of lines. Crucially, the control lines define the qubit grid, such that no local components are required. Our design enables qubit coupling beyond nearest neighbors, providing prospects for non-planar quantum error correction protocols. Fabrication is based on a three-layer design to define qubit and tunnel barrier gates. We show that a double stripline on top of the structure can drive high-fidelity single-qubit rotations. Qubit addressability and readout are enabled by self-aligned inhomogeneous magnetic fields induced by direct currents through superconducting gates. Qubit coupling is based on the exchange interaction, and we show that parallel two-qubit gates can be performed at the detuning noise insensitive point. While the architecture requires a high level of uniformity in the materials and critical dimensions to enable shared control, it stands out for its simplicity and provides prospects for large-scale quantum computation in the near future.
I. INTRODUCTION
Scaling quantum computers requires architectures that fit many qubits while avoiding an interconnect bottleneck. The paper motivates crossbar control for dense quantum-dot arrays, leveraging shared row and column lines.
- Quantum-dot spin qubits could fit billions of qubits within an area smaller than 5 × 5 mm2.
- Crossbar technology uses combinations of row and column lines to address unique grid points with few input-output connections.
- Electrons in the array can be shuttled to support nearest-neighbor operations and coupling to remote qubits.
- The proposed scheme applies crossbar control to a 2D quantum-dot array for high-fidelity operation of many qubits.
A. Crossbar network layout
The qubit module uses a three-layer crossbar gate structure with shared control lines, sparse occupation, and empty sites that support selective operation and shuttling. This simplicity depends on strong device uniformity and crosstalk compensation.
- A. Crossbar network layout: The architecture uses three in-plane gate layers with superconducting striplines above them for global RF control.
- A. Crossbar network layout: More than 1000 qubits can fit within an area smaller than 5 × 5 μm2 using 100 nm quantum-dot pitch spacing.
- A. Crossbar network layout: Sparse occupation leaves four empty neighboring dots per qubit, reducing crosstalk and enabling electron shuttling between sites.
- A. Crossbar network layout: Shared gates require high uniformity, including tunnel coupling below 10 Hz off-state and 10–100 GHz on-state operation.
- A. Crossbar network layout: Individual control of detuning and tunnel coupling requires crosstalk compensation between associated neighboring lines.
B. Magnetic field layout and ESR
Global striplines provide uniform RF driving, while alternating DC currents in column lines create frequency-selective magnetic fields. GRAPE pulses address columns despite field and resonance variations.
- B. Magnetic field layout and ESR: The low-field ESR approach uses an external out-of-plane field and global striplines rather than dense local nanomagnets.
- B. Magnetic field layout and ESR: The optimized superconducting stripline pair produces RF-field inhomogeneity below 2% across the 2D array.
- B. Magnetic field layout and ESR: Alternating direct currents through column lines create a targeted 10 MHz frequency difference between columns for qubit addressability.
- B. Magnetic field layout and ESR: A 1 nm rms gate-geometry variation contributes an estimated 100 kHz resonance linewidth, yielding total resonance variation of 150 kHz.
- B. Magnetic field layout and ESR: GRAPE pulses achieve single-qubit fidelities above 99.9%, crosstalk below 0.1%, and π/2 rotations within 250 ns.
C. Shuttling qubits for addressability and (long-range) entanglement
Independent control of detuning and tunnel coupling enables selective electron shuttling for addressability, logic, and remote swaps. Nonlinear pulsing preserves spin while supporting fast movement and phase operations.
- C. Shuttling qubits for addressability and (long-range) entanglement: Independent gate layers control detuning and tunnel coupling, enabling selective addressing at corresponding crossing points.
- C. Shuttling qubits for addressability and (long-range) entanglement: Nonlinear pulsing supports shuttling at up to at least 1 GHz with fidelity higher than 99.9%.
- C. Shuttling qubits for addressability and (long-range) entanglement: Moving a qubit to an adjacent column exploits a 10 MHz Larmor-frequency difference to implement calibrated Z-gates and phase corrections.
D. Two qubit logic gates and Pauli spin blockade based readout
The architecture uses √SWAP as its central two-qubit gate and Pauli spin blockade for spin-to-charge conversion and readout. Shuttling aligns qubits for exchange interactions and readout while exploiting symmetry-point operation and charge locking.
- Two-qubit logic gates: Shuttling qubits to the same column minimizes their resonance-frequency difference for high-fidelity √SWAP operation.The gate is performed at the charge symmetry point, where it is first-order insensitive to detuning noise, and the associated RL controls the interaction.
- Two-qubit logic gates: √SWAP is the central two-qubit gate because the considered field gradient does not sufficiently suppress SWAP-type rotations for high-fidelity CPhase gates.Together with single-qubit rotations, √SWAP provides a universal gate set; CNOT can be constructed by interleaving a Z-gate.
- Pauli spin blockade readout: Pauli spin blockade converts spin information into charge by allowing spin-up shuttling while blocking spin-down motion during adiabatic pulsing.The measurement qubit is paired with an ancillary qubit in a different magnetic-field column, creating the Zeeman-energy difference required for readout.
- Pauli spin blockade readout: 99.9% conversion fidelity can be achieved with a 3 MHz gate-pulsing speed.After conversion, the tunnel coupling is switched off so the charge state is no longer sensitive to spin relaxation before gate-based dispersive readout.
E. Parallel operation
The architecture extends local operations to line-by-line and near-global protocols by selectively controlling detuning, tunnel coupling, timing, and frequency channels. These schemes support parallel shuttling, two-qubit operations, spin-to-charge conversion, and multiplexed charge readout.
- Line-by-line operation: Selective occupation and control of ε or t0 prevent unwanted operations at untargeted quantum dots during parallel operation.Away from targets, signals are applied only to empty dots or dots with empty neighbors.
- Line-by-line operation: Line-by-line shuttling completes within 1 ns with fidelity beyond 99.9%.Parallelism occurs along one direction, while individually time-controlled control lines correct qubit-to-qubit variations and restore the intended phase.
- Line-by-line operation: Sequential line-by-line sequences preserve individual gate control for simultaneous two-qubit operations by shuttling one line, operating, shuttling back, and continuing to the next.A naïve simultaneous arrangement can make targeted qubits share gate lines, disabling the individual control needed for high-fidelity operation.
- Line-by-line operation: Spin-to-charge conversion can be performed after row shuttling with individually controlled ε and t0, while alternating shuttle directions can produce error-correction-compatible configurations.The conversion step is performed between tunnel-coupled qubits; the broader readout sequence then separates conversion from charge measurement.
- Near-global operation: 1 GHz simultaneous shuttling is possible for Δμ = 2 meV when t0 > 25 GHz, although qubit-to-qubit anticrossing variations limit the shuttle speed.Near-global shuttling without phase control can move many qubits simultaneously, while global charge readout uses frequency multiplexing and sequential detuning groups.
- Near-global operation: Sequential charge readout is independent of the number of qubits and can remain efficient for large qubit modules.The total readout time instead depends strongly on single-qubit dispersive-readout performance.
F. A network of qubit modules
The proposed large-scale architecture links many crossbar-controlled qubit modules through simpler barrier-gate-only transport structures. Moving qubit columns between modules creates a virtual array with some long-range coupling.
- Interconnected modules: A repeatable network tile connects qubit modules through extended quantum-dot grids containing barrier gates only.These transport structures reduce the required control lines but do not provide full qubit control.
- Interconnected modules: Transporting a column of qubits between module edges creates a large virtual array of coupled qubits with a degree of long-range coupling.The space between modules can accommodate local electronics or wiring fan-out.
III. DISCUSSION
The architecture addresses scalability and connectivity through shared control, long-distance shuttling, and interconnected qubit modules. These capabilities support fault-tolerant computation, non-planar connectivity, and flexible error-correction strategies, while circuit mapping and device inhomogeneity remain practical challenges.
- Interconnected modules: The architecture uses long-range shuttle highways to connect qubit modules while reducing the number of required control lines.Parallel shuttling can create space for local electronics or vertical vias between the array and external electronics.
- Error correction: The proposed architecture supports fault-tolerant universal computation and may realize error-correction schemes requiring non-planar connectivity.Within a module, its flexible layout is compatible with several topological error-correction codes, including the surface code.
- Interconnected modules: Entangling logical qubits in different modules can require shuttling only edge qubits rather than every qubit in either module.The edge qubits can be returned after performing the inter-module two-qubit operation.
- Practical challenges: Faulty or lower-performance sites may require altered codes or disabling affected modules, increasing control inhomogeneity or shuttle distances.The paper identifies qubit-to-qubit variation from the ESR stripline pair as one possible source of reduced performance.
- Practical challenges: Mapping quantum circuits onto the architecture is a particular challenge, although fast long-distance shuttling could make the architecture effectively non-planar.Such connectivity may reduce circuit overhead for algorithms requiring entanglement along extended device paths.
- Applications: The architecture is presented as a candidate for addressing connectivity problems in larger quantum simulations and for reducing circuit depth with shuttling and native √SWAP gates.These applications include moving auxiliary qubits and entangling many qubits along device paths.
Section 1. Tolerance to quantum dot inhomogeneity
Shared control requires quantum-dot uniformity in chemical potentials and tunnel couplings. The paper specifies operating ranges that suppress unwanted shuttling while enabling fast intended motion and parallel operations.
- Tunnel-coupling uniformity: Off-state tunnel coupling must remain below 10 Hz to limit unwanted electron shuttling during quantum algorithms.Unwanted shuttle events would require error correction within the surface-code operation cycle.
- Tunnel-coupling uniformity: On-state tunnel coupling must satisfy 10 GHz < ton < 100 GHz to support at least 1 GHz qubit shuttling without excessive charge-state mixing.Higher tunneling rates require larger detuning, which can increase operational overhead.
- Chemical-potential uniformity: Chemical-potential variation must satisfy Δμ < EC so quantum dots sharing a qubit line reach the same charge state.The uniform occupation configuration remains the ground state even when inter-dot tunnel coupling is turned on.
- Chemical-potential uniformity: Maintaining Δμ < EC is also important for parallel PSB because larger chemical-potential variations can shuttle electrons into adjacent columns.Correcting these errors would slow pulses and require large voltage pulses, creating significant overhead.
Section 2. Column-by-column alternating static magnetic field
The architecture uses alternating direct currents in superconducting column lines to create addressable magnetic-field patterns, while shared RF control and numerical pulse optimization support high-fidelity operations. Fabrication and device-geometry analyses quantify resonance errors, and the design extends to shuttling, readout, and spin-to-charge conversion.
- Magnetic-field design: 30 nm-wide, 60 nm-high column lines generate the alternating magnetic field evaluated in the quantum-dot plane 20 nm below the grid.The calculation assumes uniform current density because the effective superconducting penetration depth can exceed the gate dimensions.
- Fabrication tolerance: 1 nm fabrication or geometry error produces a maximum resonance-frequency change of 100 kHz, with column-line height the limiting dimension.The reported change is weakly dependent on quantum-dot size.
- Fabrication tolerance: Finite-dot-size averaging provides an upper-bound estimate because the dot center is least sensitive to fabrication errors, while larger dots generally increase field deviations.The analysis uses linear averages, although the real electron wave function is more concentrated near the center.
- Single-qubit control: GRAPE pulses achieve fidelities beyond 99.9% across up to 300 kHz resonance-frequency variation and over 3% ESR-field variation in 250 ns.The optimized pulse requires 1.1 MHz RMS amplitude versus 0.7 MHz for the reference pulse and reaches a maximum peak of approximately 3 MHz.
- Shuttling and readout: The shuttling analysis combines detuning, tunnel-coupling, and speed constraints, requiring 26 meV detuning for t0 = 100 GHz and 99.9% charge-state fraction.For global shuttling with Δμ = 2 meV, the minimum tunnel coupling is greater than 20 GHz; multiplexed readout requires approximately 16 measurement cycles at t0,min = 10 GHz.
- Spin-to-charge conversion: A 3 MHz PSB spin-to-charge conversion reaches high fidelity using 200 ns tunnel turn-on, 110 ns linear detuning sweep, and 20 ns tunnel turn-off.The conversion analysis assumes long spin lifetimes and identifies a fidelity-beyond-99.9% operating region.
- Shuttling between modules: Grouped shuttling gates can move individual qubits or complete arrays between module sites while reducing external wiring.The scheme repeats directional barrier operations and connects gates performing similar operations together.