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X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories

Amogh Agrawal, Akhilesh Jaiswal, Chankyu Lee, Kaushik Roy

arXiv:1712.05096v2cs.ET

TL;DR

Von-Neumann systems incur energy and throughput costs from frequent processor–memory transfers, motivating in-memory Boolean computation. The paper introduces X-SRAM, augmented CMOS 8T and 8+T SRAM cells supporting vector Boolean operations and direct read-compute-store, and verifies feasibility through predictive models and variation analysis.

  • Problem

    Frequent transfers between physically separate memory and compute units limit energy efficiency and throughput, especially for data-intensive applications.

  • Method

    X-SRAM augments standard CMOS 8T and 8+T Differential SRAM cells with peripheral schemes for vector NAND, NOR, IMP, XOR, and read-compute-store operations.

  • Results

    The proposed operations were verified using predictive transistor models and Monte-Carlo variation analysis, while an encryption example reduced memory accesses by up to 74.7% for 128b keys and 74.6% for 256b keys in ECB mode.

  • Takeaways & Limitations

    X-SRAM extends SRAM arrays with in-memory Boolean computation while preserving ordinary memory functionality and enabling direct storage of computed results.

Abstract

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Silicon-based Static Random Access Memories (SRAM) and digital Boolean logic have been the workhorse of the state-of-art computing platforms. Despite tremendous strides in scaling the ubiquitous metal-oxide-semiconductor transistor, the underlying \textit{von-Neumann} computing architecture has remained unchanged. The limited throughput and energy-efficiency of the state-of-art computing systems, to a large extent, results from the well-known \textit{von-Neumann bottleneck}. The energy and throughput inefficiency of the von-Neumann machines have been accentuated in recent times due to the present emphasis on data-intensive applications like artificial intelligence, machine learning \textit{etc}. A possible approach towards mitigating the overhead associated with the von-Neumann bottleneck is to enable \textit{in-memory} Boolean computations. In this manuscript, we present an augmented version of the conventional SRAM bit-cells, called \textit{the X-SRAM}, with the ability to perform in-memory, vector Boolean computations, in addition to the usual memory storage operations. We propose at least six different schemes for enabling in-memory vector computations including NAND, NOR, IMP (implication), XOR logic gates with respect to different bit-cell topologies $-$ the 8T cell and the 8$^+$T Differential cell. In addition, we also present a novel \textit{`read-compute-store'} scheme, wherein the computed Boolean function can be directly stored in the memory without the need of latching the data and carrying out a subsequent write operation. The feasibility of the proposed schemes has been verified using predictive transistor models and Monte-Carlo variation analysis.

I. INTRODUCTION

The paper motivates in-memory Boolean computation as a response to energy and throughput costs from processor–memory transfers, and introduces X-SRAM schemes using CMOS 8T and 8+T cells.

  • Frequent data transfers between separate memory and compute units increase energy overhead and limit throughput in von-Neumann systems.
  • In-memory computing embeds logic in the memory array to reduce memory–processor transfers while retaining standard storage functionality.
  • For 8+T cells, the paper proposes NAND, NOR, and XOR using asymmetric differential sense amplifiers, alongside read-compute-store operation for both cell types.
  • The paper explores at least six Boolean-computation techniques in standard CMOS 8T and 8+T Differential SRAM cells with minimal peripheral modifications.
  • For 8T cells, the work uses skewed-inverter sensing for NAND, NOR, and XOR, plus voltage-divider operation for IMP and XOR.

WWL WWL

The proposed SRAM extensions support digital vector Boolean operations through isolated read ports and shared peripheral circuitry, with read-compute-store enabling direct result storage.

  • 8+T cells implement NAND, NOR, and XOR with asymmetric sense amplifiers while preserving usual memory read/write functionality.
  • 8T and 8+T cells exploit isolated read ports and separate read/write paths to embed Boolean logic with minimal peripheral changes.
  • The 8T cell supports NAND, NOR, IMP, and XOR through multiple sensing and voltage-divider schemes.
  • The read-compute-store scheme directly writes computed Boolean results into a target row without latching the output or performing a subsequent write operation.
  • The proposals are evaluated with SPICE transient simulations and Monte-Carlo analyses including threshold-voltage, temperature, and supply-voltage variations.

A. 8-Transistor SRAM: NOR operation

The 8T cell performs NOR by simultaneously activating read word-lines and sensing whether the shared read bit-line remains precharged.

  • The decoupled 8T read port permits simultaneous activation of two read word-lines without read-disturb concerns.
  • Monte-Carlo SPICE simulations evaluate NAND and NOR outputs for all input cases under 30mV sigma threshold-voltage variation.
  • The shared read bit-line remains high only when both operand bits are ‘0’, representing the NOR condition.
  • Gated skewed inverters convert the read bit-line state into the NOR output without significant additional circuitry.
  • Activating n read word-lines generalizes the mechanism to an n-input NOR truth table.

B. 8-Transistor SRAM: NAND operation

The 8T SRAM topology supports in-memory NAND, NOR, IMP, and XOR operations by exploiting isolated read paths, discharge behavior, and voltage-divider sensing. Monte-Carlo simulations assess these schemes under transistor, process, temperature, and supply variations.

  • NAND and NOR: Timing the read-word-line pulse preserves a voltage difference between ‘01/10’ and ‘11’, allowing an inverter threshold to distinguish NAND inputs.The NAND scheme has a narrower design margin because its operation depends on discharge timing.
  • Logic operations: NORing the AND and NOR outputs produces XOR, extending the 8T bit-cell’s in-memory logic beyond NAND and NOR.The paper identifies IMP and XOR as additional operations enabled through the voltage-divider scheme.
  • Voltage-divider scheme: The voltage-divider scheme uses source-line biasing and a precharged read bit-line to encode operand combinations for IMP and XOR sensing.During computation, SL1 is pulled to VDD, SL2 is grounded, and RDBL is precharged to Vpre = 400mV.
  • Variation analysis: Verror is close to zero in Monte-Carlo analysis, indicating that the voltage-divider configuration remains robust under process, temperature, supply, and precharge variations.The simulations include 30mV sigma threshold-voltage variation and account for variations in Vpre.
  • Voltage-divider scheme: IMP is universal, while the voltage-divider outputs can also identify ‘01’ and ‘10’ during the computation, supporting a two-bit read in 50% of cases.When neither inverter output is high, a subsequent read is needed to distinguish ‘00’ from ‘11’.

D. Proposed ‘read-compute-store’ (RCS) scheme

The read-compute-store scheme uses the 8T cell’s decoupled read and write ports to compute a Boolean function and store its result in a third row during the same cycle. This removes the need to latch the result and perform a later write.

  • RCS operation: RCS simultaneously reads two operand rows through RWL1 and RWL2 while enabling a third row’s WWL to store the computed Boolean output.The scheme can compute NAND, NOR, IMP, or XOR while writing the result to the third row.
  • RCS significance: The 8T cell’s decoupled read-write ports allow computation and storage to proceed concurrently instead of requiring a multi-cycle latch-then-write sequence.The paper notes that the 8T write port is specifically optimized for writing.
  • RCS implementation: A compute block selects the Boolean output through a multiplexer and feeds the write drivers connected to the destination row.For the NAND example, RWL1, RWL2, and WWL3 are activated simultaneously, storing the result in Cell 3.

III. 8+ TRANSISTOR DIFFERENTIAL READ SRAM

The 8+T Differential SRAM enables in-memory logic using differential read bit-lines and asymmetric sense amplifiers. Its differential sensing supports NAND, NOR, AND, and XOR operations while retaining regular memory-read functionality and improving robustness over single-ended sensing.

  • Cell topology: The 8+T Differential SRAM separates read and write paths and senses complementary RBL/RBLB voltages through differential readout.A ninth transistor shares the read-word-line across cells in a row.
  • Read behavior: For operand cases ‘00’ and ‘11’, one read bit-line discharges while the other remains precharged; for ‘01’ and ‘10’, both discharge.The four discharge cases form the timing basis for differential in-memory computation.
  • Logic operations: Asymmetric sense amplifiers distinguish operand patterns by deliberately sizing one transistor larger, producing NAND or NOR outputs from the differential read signals.Parallel sense amplifiers provide AND/NAND and OR/NOR outputs, while an additional NOR combines them into XOR.
  • Variation analysis: The differential voltage Vdiff should be near 0V for ‘01/10’ but large for ‘11/00’, allowing sense-amplifier asymmetry to resolve the former and differential voltage to resolve the latter.Monte-Carlo analysis evaluates Vdiff under 30mV sigma threshold-voltage variation, temperature changes, supply variation, and process corners.
  • Memory functionality: The two asymmetric sense amplifiers also support ordinary memory reads, and their XOR output acts as an in-memory check for possible read failures.The RCS scheme can be applied to the 8+T Differential SRAM because its read and write paths are decoupled.
  • Robustness: Differential read sensing makes 8+T cells more robust for in-memory bit-wise logic than conventional 8T cells with single-ended sensing.The proposed asymmetric sense amplifiers do not disturb the SRAM cell’s usual read/write functionality and can be shared between normal reads and in-memory operations.

IV. DISCUSSIONS

The discussion compares X-SRAM proposals across 8T and 8+T Differential cells, emphasizing trade-offs among sensing robustness, port separation, area, and application-dependent Boolean functions.

  • Cell-level trade-offs: The 8T cell supports separate read/write ports and read-compute-store, but its single-ended sensing raises robustness concerns.These properties distinguish its operational flexibility from its sensing limitation.
  • Cell-level trade-offs: The 8+T cell combines differential sensing with separate read/write ports, while shared diffusion tracks preserve an area per-bit similar to standard 8T.It uses six diffusion tracks versus five for standard 8T, with the outer tracks shared by adjacent cells.
  • Comparison with 6T: NOR, NAND, and XOR can also be implemented in 6T arrays, but sequential word-line activation and read-disturb susceptibility reduce robustness relative to 8T and 8+T.The 6T cell’s shared read-write paths prevent simultaneous word-line activation.
  • Application scope: The choice of bit-cell and Boolean function depends heavily on the target application, with possible deployment in processors, GPUs, and machine-learning hardware.The manuscript describes replacing SRAM blocks or register files with X-SRAM arrays in these systems.
  • Proposal comparison: Table I summarizes average energy per bit, latency, and the advantages and disadvantages of the proposed in-memory techniques.The table organizes the design trade-offs across the different bit-cell and logic proposals.

V. X-SRAM BASED NON-STANDARD VON-NEUMANN COMPUTING FOR AES ENCRYPTION

The paper evaluates X-SRAM as a memory block in a von-Neumann AES system, where custom in-memory instructions replace some conventional memory traffic. The evaluation examines normalized accesses across AES modes and key sizes.

  • System-level evaluation: X-SRAM adds massively parallel vector Boolean operations within the memory block to reduce energy-expensive data movements over the system bus.The AES case study assesses system-level implications of replacing conventional SRAM with X-SRAM.
  • Evaluation setup: Figure 14 compares normalized memory accesses for AES encryption and decryption modes with and without X-SRAM custom in-memory instructions.The accesses are divided among memory reads, memory writes, and custom in-memory instructions.

A. Simulation Methodology

The simulation uses a Nios-II-based von-Neumann system extended with X-SRAM custom instructions and software macros that replace repetitive Boolean operations.

  • System implementation: The simulated system contains a processor, data memory, and instruction memory connected by a shared bus.The system uses Intel’s programmable Nios-II processor and the Avalon memory-mapped protocol.
  • System implementation: The instruction set is extended with X-SRAM custom instructions, and the bus architecture supports passing three addresses at a time.These instructions are enabled by the proposed X-SRAM operations.
  • In-memory parallelism: X-SRAM performs bit-wise operations across memory-array rows, enabling multiple computations in parallel when rows store multiple data words.This data parallelism is illustrated for arrays accessed through a shared bus.
  • Software configuration: Software replaces repetitive Boolean operations with custom instruction macros.The macros allow the AES software to invoke the added in-memory instructions.

B. Results and Discussion

Across AES modes and key sizes, X-SRAM custom instructions reduce normalized memory accesses relative to conventional SRAM. The paper attributes this reduction to lower memory traffic and reports associated system-level implications.

  • Evaluation scope: Three AES modes—CBC, CTR, and ECB—are evaluated for 128-bit and 256-bit keys.The study counts memory reads, memory writes, and custom in-memory instructions for encryption and decryption.
  • Memory-access results: 74.7% and 74.6% reductions in memory accesses are reported for ECB with 128-bit and 256-bit keys, respectively.The results are normalized to the memory accesses of a conventional SRAM block without custom in-memory instructions.
  • Energy implications: Reducing memory transactions is reported to save approximately 75% of memory-access energy consumption and reduce peripheral-circuit energy.The paper links fewer accesses to lower transaction-related energy use.
  • System implications: Fewer accesses can reduce arbitration wait times on a shared bus and alleviate limited bus bandwidth while preserving memory bandwidth for parallelism.These implications are presented for systems with multiple masters sharing the bus.
  • Overall result: The proposed Boolean operations and read-compute-store scheme are supported by Monte-Carlo simulations using predictive transistor models, while AES demonstrates up to 75% fewer memory transactions.The conclusion summarizes both circuit-level verification and the system-level case study.

APPENDIX

The standard 6T SRAM performs reads through pre-charged differential bit-lines, while sequential word-line pulses enable vector Boolean operations without simultaneous activation. Asymmetric sense amplifiers produce NAND/AND, NOR/OR, and XOR outputs, with reported 29.3fJ per bit and 3ns latency.

  • 6T SRAM read operation: 6T SRAM reads pre-charge BL and BLB to VDD, then sense the differential voltage after enabling the selected row.Depending on the stored bit, BL or BLB discharges before differential sensing.
  • Sequential word-line activation: Sequentially pulsed word-lines activate rows storing A and B in sequence to avoid read-disturb risks from simultaneous activation.The address decoder turns WL1 and WL2 on consecutively for the two operand rows.
  • Sequential word-line activation: For inputs ‘01’ and ‘10’, both bit-lines settle near VDD/2, whereas equal inputs produce a stronger discharge on one bit-line.The pulse duration is selected so each individual pulse reduces BL/BLB to approximately VDD/2.
  • Boolean sensing: 29.3fJ per bit and 3ns are the reported average energy consumption and latency for 6T-SRAM in-memory operations.The same sensing sequence supports NAND/AND, NOR/OR, and XOR bit-wise operations through parallel asymmetric sense amplifiers.
  • Robustness evaluation: Monte-Carlo SPICE simulations with 30mV threshold-voltage sigma variations evaluate asymmetric-sense-amplifier outputs for all four input cases.The simulated outputs are SANAND and SANOR for ‘00,01,10,11’.

B. 6T SRAM: Copy Operation

The 6T SRAM copy scheme combines a source read with a destination write using shared bit-lines, reducing the copy to one memory transaction. Because the write is weak, boosted destination word-line voltage is required, and 8T/8+T cells require a different read-compute-store approach.

  • Copy motivation: The proposed 6T copy operation replaces separate processor read and write transactions with a source-to-destination transfer using coupled read-write paths.The conventional sequence performs a memory read followed by a memory write, whereas the proposed scheme targets one transaction.
  • Copy validation: Fig. 19(c) presents the Monte-Carlo simulation used to test the proposed copy operation.The simulation results correspond to the final state of Cell 2.
  • Copy procedure: Cell 1 and Cell 2 connect to WL1 and WL2; pre-charged BL/BLB first read Cell 1 before the destination cell is written.For a source storing ‘1’, BL remains at VDD while BLB discharges to 0V.
  • Copy limitation: The copy’s write phase is weak because the charge on BL/BLB switches the destination state, so boosted WL2 voltage is required to prevent write failures.The paper reports a 30mV sigma threshold-voltage variation Monte-Carlo test using 45-nm PTM models.
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