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8T SRAM Cell as a Multi-bit Dot Product Engine for Beyond von-Neumann Computing

Akhilesh Jaiswal, Indranil Chakraborty, Amogh Agrawal, Kaushik Roy

arXiv:1802.08601v2cs.ET

TL;DR

The paper addresses the energy and throughput costs of moving data between separate memory and compute units, along with practical barriers to memristive implementations. It configures standard 8T SRAM arrays for analog-like multi-bit dot products using two read-port voltage configurations and sensed output currents. The resulting array retains ordinary digital storage and read-write operation while serving as a dedicated or on-demand dot-product accelerator.

  • Problem

    Separate memory and compute units create costly data transfers and bandwidth limits, while memristive dot-product approaches face manufacturing and endurance challenges.

  • Method

    The paper applies analog voltages to 8T SRAM read ports, senses output currents, and uses two configurations plus read-transistor sizing to compute multi-bit dot products.

  • Results

    The proposed 8T SRAM dot-product engine can be integrated into neural-network frameworks without significant performance loss while retaining standard digital memory use.

  • Takeaways & Limitations

    An 8T SRAM array can serve as either a dedicated dot-product engine or an on-demand accelerator alongside its normal storage function.

Abstract

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Large scale digital computing almost exclusively relies on the von-Neumann architecture which comprises of separate units for storage and computations. The energy expensive transfer of data from the memory units to the computing cores results in the well-known von-Neumann bottleneck. Various approaches aimed towards bypassing the von-Neumann bottleneck are being extensively explored in the literature. Emerging non-volatile memristive technologies have been shown to be very efficient in computing analog dot products in an in-situ fashion. The memristive analog computation of the dot product results in much faster operation as opposed to digital vector in-memory bit-wise Boolean computations. However, challenges with respect to large scale manufacturing coupled with the limited endurance of memristors have hindered rapid commercialization of memristive based computing solutions. In this work, we show that the standard 8 transistor (8T) digital SRAM array can be configured as an analog-like in-memory multi-bit dot product engine. By applying appropriate analog voltages to the read-ports of the 8T SRAM array, and sensing the output current, an approximate analog-digital dot-product engine can be implemented. We present two different configurations for enabling multi-bit dot product computations in the 8T SRAM cell array, without modifying the standard bit-cell structure. Since our proposal preserves the standard 8T-SRAM array structure, it can be used as a storage element with standard read-write instructions, and also as an on-demand analog-like dot product accelerator.

I. INTRODUCTION

The von-Neumann separation of storage and computation causes costly data movement and bandwidth limits, motivating in-memory dot-product computation. This work uses conventional 8T SRAM to provide analog-like dot products while retaining standard memory functionality.

  • I. INTRODUCTION: Frequent transfers between separate memory and compute units consume substantial energy and limit throughput for data-intensive applications.The bottleneck is particularly relevant to machine learning and artificial intelligence workloads.
  • I. INTRODUCTION: In-memory computing intertwines storage and computation to increase throughput by performing operations inside the memory array.
  • I. INTRODUCTION: Prior SRAM approaches emphasized Boolean operations or 6T analog computation, whereas dot products remain a central workload and 6T designs face read-disturb constraints.The cited 6T analog methods rely on accumulated bit-line voltage, creating a constrained design space.
  • I. INTRODUCTION: The paper shows that an unmodified conventional 8T SRAM cell can support analog-like dot-product computation through two configurations.The read-port transistor sizing is adjusted, while the basic bit-cell circuitry remains unchanged.

WWL WWL

The proposed 8T SRAM array preserves conventional storage behavior while supporting analog-like dot-product acceleration. Its two configurations and non-idealities are evaluated through detailed 45nm simulation analysis.

  • WWL WWL: Two configurations enable dot-product computation without modifying the basic 8T bit-cell circuitry.
  • WWL WWL: The 8T SRAM array can operate as either a conventional digital memory or an on-demand analog-like dot-product accelerator.The standard read-write functionality is retained because the basic bit-cell structure remains unaltered.
  • WWL WWL: Detailed 45nm predictive-model simulations include layout analysis and non-idealities such as line resistance and threshold-voltage variation.The analysis highlights trade-offs between the proposed configurations.

II. 8T-SRAM AS A DOT PRODUCT ENGINE

The 8T SRAM read port converts analog input voltages and stored digital weights into summed output currents, supporting multi-bit dot products through transistor sizing. Config-A applies inputs to source lines, while Config-B applies them to read word lines and trades current behavior against other constraints.

  • II. 8T-SRAM AS A DOT PRODUCT ENGINE: The 8T cell uses a decoupled read port while retaining separate write operation, allowing dot-product computation without affecting stored-bit stability.
  • II. 8T-SRAM AS A DOT PRODUCT ENGINE: Analog inputs applied to shared source lines produce column currents proportional to weighted sums of the inputs in Config-A.Stored bits select ON or OFF conductance, and the common read bit-line sums currents across rows.
  • II. 8T-SRAM AS A DOT PRODUCT ENGINE: Four-bit weights are represented by read-transistor conductance ratios of 8 : 4 : 2 : 1 across grouped columns.Summing the four column currents yields the required weighted dot product.
  • II. 8T-SRAM AS A DOT PRODUCT ENGINE: Lowering the SRAM supply voltage reduces static current caused by transistor ON resistance that is lower than typical memristor ON resistance.The 8T cell is described as retaining robust operation at highly scaled supply voltages.
  • II. 8T-SRAM AS A DOT PRODUCT ENGINE: Config-B applies analog inputs to the read word lines with a constant source-line bias and relies on a voltage range where output current varies linearly with input.The same transistor-sizing strategy provides multi-bit precision through conductance weighting.
  • II. 8T-SRAM AS A DOT PRODUCT ENGINE: Output-current sensing with a resistor can perturb the read-bit-line voltage and thereby alter transistor conductance and the desired current.

III. RESULTS

The proposed 8T-SRAM dot-product engine exhibits linear current responses to analog inputs and multi-bit weights, while circuit techniques mitigate multi-row deviation and preserve neural-network accuracy. Simulations also identify current, area, and interconnect-related constraints.

  • Simulation setup: The engine was evaluated with HSPICE using 45nm predictive technology models and a 0.65V SRAM supply.The analysis included sensing resistance and examined both proposed configurations.
  • Single-cell characteristics: IRBL varies linearly with 4-bit weight levels in both configurations when input voltages remain within their respective linear regions.The evaluated Config. A voltages were 0.05V, 0.1V, and 0.15V; Config. B used 0.5V, 0.55V, and 0.6V.
  • Multi-row operation: Without op-amp termination, summed IRBL increasingly deviates from the ideal N × I1 response as more rows are activated, reaching nearly 6mA for 64 worst-case rows.The deviation arises from sensing-resistance-induced VBL changes that alter effective cell conductance.
  • Multi-row operation: Op-amp termination mitigated summed-current deviation from ideal behavior across increasing row counts, although 64-row current still exceeded the RBL electromigration limit.Clamping VBL at Vpos reduces current and preserves weight-level linearity, but does not eliminate the high-current constraint.
  • Layout analysis: The 4-bit implementation increases total SRAM-array area by approximately 29.4% relative to a standard 8T-SRAM array.Read-transistor sizing and an additional source-line metal route produce the reported overhead; multi-VT design could reduce it.

IV. VARIATION ANALYSIS

The variation analysis evaluates how source/bit-line resistance and transistor threshold-voltage variation affect output-current accuracy in the proposed dot-product engine.

  • The analysis considers source-line and bit-line resistances together with transistor threshold-voltage variations as the principal non-idealities.

A. Effect of Line-Resistances

Line resistance causes data- and position-dependent current errors, so the study compares configurations and activation patterns under worst-case and neural-network-relevant conditions.

  • Worst-case line-resistance error occurs when all inputs and weights are at their highest values, maximizing current and parasitic voltage drops.
  • Config. B reduces line-resistance error by driving the source line from both ends or tapping it every 16 bits, unlike Config. A.Tapping is feasible for Config. B because its source line uses a global bias voltage; it is infeasible for Config. A.
  • The proposed 4-bit array layout sizes read transistors in an 8:4:2:1 ratio and adds a source-line metal route, incurring approximately 29.4% area overhead.
  • In trained neural-network weight distributions, relevant lower weight levels have approximately 0–5% error for 16 rows and 0–3.4% for 8 rows.
  • For Config. B with taps every 16 columns and both-end driving, worst-case current error stays within 9% and improves when inputs or weights decrease.

B. VT Variations

The threshold-voltage study uses Monte Carlo simulations to quantify output-current variation across input voltages, weight levels, and current magnitudes.

  • 1000 Monte Carlo simulations evaluate output-current variation for input voltages from 0.35V to 0.675V and weight levels from 0 to 15.
  • Threshold-voltage variation produces larger standard deviation at higher output current for 16 activated rows.The analysis uses 30 mV threshold-voltage variation for the minimum-sized transistor and scales it with transistor width.
  • The current-variation analysis omits line resistance because including it would make deviations both spatially dependent and difficult to analyze, while prior worst-case errors were acceptable.

V. DISCUSSIONS

The discussion positions the SRAM array as an application-dependent in-situ dot-product engine whose practical benefits depend on peripheral-circuit requirements and access strategy.

  • The engine targets approximate vector multiplication and addition beyond neural networks, with peripheral complexity depending strongly on the application.
  • For a 16×16 dot product, the proposed engine performs the computation in one instruction instead of sequential digital row access and MAC operations.
  • DACs, ADCs, and other peripheral circuits dominate the dot-product engine’s total energy consumption.

VI. CONCLUSION

The work presents 8T SRAM as a vector-matrix dot-product engine supporting analog-like multi-bit computation while preserving ordinary digital memory operation.

  • 8T SRAM supports analog-like multi-bit vector-matrix dot products while retaining normal digital read and write operations.The cell can operate either as a dedicated dot-product engine or as an on-demand accelerator.
  • Two 8T-SRAM configurations enable the proposed dot-product computations, with trade-offs identified between them.The work highlights configuration-specific trade-offs rather than selecting a single universally preferable design.
  • The approach extends 8T-cell applicability to data-intensive algorithms, including machine learning and artificial intelligence.The stated motivation is that dot products are widely used in these applications.
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