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SgxPectre Attacks: Stealing Intel Secrets from SGX Enclaves via Speculative Execution

Guoxing Chen, Sanchuan Chen, Yuan Xiao, Yinqian Zhang, Zhiqiang Lin, Ten H. Lai

arXiv:1802.09085v3cs.CR

TL;DR

The paper asks whether speculative-execution vulnerabilities undermine SGX’s confidentiality and integrity guarantees. It develops SgxPectre Attacks using branch-prediction injection, race-winning techniques, and automated gadget discovery, and demonstrates recovery of enclave and Intel platform secrets. The authors conclude that vulnerable SGX processors are no longer trustworthy, while noting that unpatched processors and legacy sealed secrets remain exposed.

  • Problem

    The paper investigates whether recently disclosed out-of-order and speculative-execution vulnerabilities compromise SGX’s protected execution environments.

  • Method

    The paper combines branch-target injection, techniques for winning speculative-execution races, and dynamic symbolic execution to identify exploitable enclave gadgets.

  • Results

    SgxPectre Attacks compromise enclave confidentiality and integrity, recover enclave memory and register values, and extract seal and attestation keys from Intel-signed enclaves.

  • Takeaways & Limitations

    The paper concludes that SGX processors affected by these hardware vulnerabilities are no longer trustworthy and urges enclave developers to verify vulnerabilities before deployment.

  • Takeaways & Limitations

    Secrets provisioned to unpatched processors and legacy sealed secrets remain vulnerable even when Intel’s IBRS patch and attestation defenses are effective.

Abstract

from arXiv · show

This paper presents SgxPectre Attacks that exploit the recently disclosed CPU bugs to subvert the confidentiality and integrity of SGX enclaves. Particularly, we show that when branch prediction of the enclave code can be influenced by programs outside the enclave, the control flow of the enclave program can be temporarily altered to execute instructions that lead to observable cache-state changes. An adversary observing such changes can learn secrets inside the enclave memory or its internal registers, thus completely defeating the confidentiality guarantee offered by SGX. To demonstrate the practicality of our SgxPectre Attacks, we have systematically explored the possible attack vectors of branch target injection, approaches to win the race condition during enclave's speculative execution, and techniques to automatically search for code patterns required for launching the attacks. Our study suggests that any enclave program could be vulnerable to SgxPectre Attacks since the desired code patterns are available in most SGX runtimes (e.g., Intel SGX SDK, Rust-SGX, and Graphene-SGX). Most importantly, we have applied SgxPectre Attacks to steal seal keys and attestation keys from Intel signed quoting enclaves. The seal key can be used to decrypt sealed storage outside the enclaves and forge valid sealed data; the attestation key can be used to forge attestation signatures. For these reasons, SgxPectre Attacks practically defeat SGX's security protection. This paper also systematically evaluates Intel's existing countermeasures against SgxPectre Attacks and discusses the security implications.

1 INTRODUCTION

SGX isolates sensitive code and data, but speculative-execution vulnerabilities raise fundamental questions about whether that protection still holds. The paper introduces SgxPectre Attacks and demonstrates practical breaches of enclave and Intel platform secrets.

  • Motivation: SGX places sensitive components in enclaves designed to isolate code and data from software outside the enclave.The platform also provides memory encryption, sealed storage, and remote attestation.
  • Motivation: CPU vulnerabilities from out-of-order and speculative execution allow attackers to extract content otherwise accessible only to privileged software, motivating a security analysis of SGX.The paper specifically examines whether SGX retains its security promises after Meltdown and Spectre.
  • Attack overview: SgxPectre exploits a race between injected speculative memory references, observable cache traces, and branch-resolution latency.The attack differs from traditional enclave side channels in its threat model, attack vectors, race-winning techniques, and consequences.
  • Findings: Vulnerable patterns in common SGX runtimes enable attacks against arbitrary enclave programs that recover enclave memory contents and internal register values.The paper reports end-to-end attacks against victim enclaves developed by independent software vendors.
  • Findings: SgxPectre can steal provisioning, seal, and attestation keys, enabling sealed-storage decryption or modification and extraction of Intel’s attestation key.The authors demonstrated extraction of Intel’s seal key from a quoting enclave and used it to decrypt the sealed EPID blob.
  • Countermeasures: Intel’s IBRS microcode update can cleanse branch-prediction history at enclave boundaries, while remote attestation rejects signatures from unpatched CPUs as outdated.The paper also reports that secrets provisioned to unpatched processors remain exposed and that the EPID private key can be extracted.

2 BACKGROUND

The background describes processor speculation and implicit caching, then explains SGX’s enclave protections, lifecycle, key mechanisms, and cache-based side channels.

  • 2.1 Intel Processor Internals: Out-of-order execution allows instructions to execute concurrently and retire in program order to resolve inaccuracies caused by execution dependencies.Retirement preserves architectural ordering despite differing instruction completion times.
  • 2.1 Intel Processor Internals: Speculative execution predicts uncertain control flow, using branch-prediction hardware such as branch target buffers and return stack buffers.Correct predictions may retire, while mispredicted execution is rewound.
  • 2.1 Intel Processor Internals: Implicit caching stores instructions or data fetched through mechanisms such as prefetching, branch prediction, and TLB miss handling.Mispredicted branches can trigger unintended instruction fetches and memory accesses, making implicit caching a root cause of the studied CPU vulnerabilities.
  • 2.2 Intel SGX: SGX creates processor-maintained enclaves whose memory confidentiality and integrity are protected from untrusted system software.Its security primitives include isolation, encryption, sealed storage, and remote attestation.
  • 2.2 Intel SGX: EENTER starts enclave execution at a TCS-specified instruction, while asynchronous exits save execution state in the enclave’s State Save Area before control returns outside.Multiple TCSs support multithreading inside an enclave.
  • 2.2 Intel SGX: SGX uses CPUSVN to track microcode security versions, derives seal keys through EGETKEY, and uses EPID private keys for remote attestation.Older CPUSVNs support access to legacy sealed secrets, whereas newer CPUSVNs cannot be selected for deriving seal keys.

3 THREAT MODEL

The threat model gives the adversary system-level control, interaction with the target enclave, and the ability to run a controlled enclave that poisons branch-prediction state.

  • 3 THREAT MODEL: The adversary has complete control of the operating system, including recompiling the kernel and rebooting with arbitrary arguments.This establishes system privilege over the machine running the SGX processor.
  • 3 THREAT MODEL: The adversary can launch the target enclave through a controlled software program and control ECall arguments and OCall return values.These interfaces provide interaction with the targeted enclave.
  • 3 THREAT MODEL: The adversary can run a fully controlled enclave in the same or another process, allowing poisoning of BTB entries used by the target enclave.The attack assumes the target enclave binary is known and unchanged during execution.

4 SGXPECTRE ATTACKS

SgxPectre Attacks poison branch prediction to redirect enclave control flow speculatively, then recover secrets from cache traces. The attack depends on winning a race before branch resolution and can use several external branch-injection paths and side channels.

  • 4.1 A Simple Example: SgxPectre Attacks use BTB poisoning to make an enclave branch speculatively target instructions that may leak secrets.The attack begins by repeatedly training an indirect branch so its predicted target points to secret-leaking enclave instructions.
  • 4.1 A Simple Example: The attacker prepares execution by delaying branch retirement and forcing return prediction through the BTB before entering the enclave.Preparation includes flushing the victim branch target and depleting the return stack buffer, while enclave memory cannot be flushed directly with clflush.
  • 4.1 A Simple Example: The attacker controls registers so speculative instructions read a chosen enclave secret and use it to touch an entry in a monitored external array.In the example, r14 points to the secret and r15 points to the monitored array; the resulting access encodes the secret in the cache.
  • 4.4 Leaking Secrets via Side Channels: A Flush-Reload scan of the monitored array reveals which entry was cached and therefore extracts the secret value.The adversary flushes the array before execution, reloads its entries afterward, and measures reload latency.
  • 4.2 Injecting Branch Targets into Enclaves: BTB poisoning can originate outside the enclave, including from the same process, because Intel processors use lower virtual-address bits for BTB indexing and tagging.The paper also examines poisoning from a different process and describes EENTER/ECall control flow as an attack surface for entering enclave code.
  • 4.4 Leaking Secrets via Side Channels: Speculative execution leaves implicit cache effects even after incorrect instructions are discarded, enabling cache-based leakage from enclave execution.Traditional enclave cache attacks require secret-dependent access patterns, whereas SgxPectre can force speculative references to touch memory outside the enclave.
  • 4.4 Leaking Secrets via Side Channels: Page-fault side channels cannot be used for SgxPectre because speculatively executed instructions do not raise exceptions.The paper identifies BTB, TLB, and DRAM-cache channels as theoretically usable alternatives.
  • 4.5 Winning a Race Condition: The attack’s central race succeeds only when speculative secret-leaking memory accesses complete before the targeted branch retires.The desired access pattern includes branch access D1, instruction fetch I1, and data accesses D2 and D3; enclave translations may require cached page-table copies.

5 ATTACK GADGETS IDENTIFICATION

The paper identifies exploitable SgxPectre instruction patterns and develops automated symbolic execution to find them in enclave binaries. The method finds relevant gadgets across Intel SGX SDK, Graphene-SGX, and Rust-SGX runtimes.

  • 5 ATTACK GADGETS IDENTIFICATION: Existing SGX runtime libraries contain code patterns that make enclave programs vulnerable to SgxPectre Attacks.The authors report finding these patterns in Intel SGX SDK, Graphene-SGX, and Rust-SGX.
  • 5.1 Types of Gadgets: SgxPectre exploitation requires a Type-I branch-control pattern and a Type-II pair of memory references that reveals enclave data through a cache side channel.Type-I gadgets provide an attacker-influenced branch and controlled registers; Type-II gadgets connect a secret load to a dependent memory access.
  • 5.1.1 Type-I gadgets: branch target injection.: A Type-I gadget begins at EENTER’s enclave_entry and ends at an indirect jump, indirect call, or near return.Its exploitability increases with the number of registers controlled by the adversary when the branch executes, relaxing restrictions on Type-II gadgets.
  • 5.1.2 Type-II gadgets: secret leaking: A Type-II gadget loads enclave data through regA into regB, then uses regB to determine a later memory-reference address whose cache effect leaks the value.The speculative sequence is discarded, but the second reference’s implicit caching remains observable through Flush-Reload.
  • 5.2 Automated Gadget Identification: Manual gadget discovery is tedious and error-prone, motivating automated binary scanning before enclave deployment.The paper seeks to detect and eliminate exploitable gadgets in enclave binaries on untrusted SGX machines.
  • 5.2 Automated Gadget Identification: Dynamic symbolic execution enables automated gadget identification by exploring symbolic inputs, execution paths, and machine states.The implementation uses symbolic execution to represent registers, stacks, and memory while examining possible enclave behaviors.
  • 5.3 Gadget Identification: The tool scans nearby memory references for potential Type-II gadgets, then symbolically validates whether the later address derives from the loaded value.It checks symbolic relationships involving regB and, when present, whether regC retains its original symbolic value.
  • 5.3 Gadget Identification: The analysis starts from enclave_entry for ECall gadgets and from OCall interfaces or 37 Graphene-SGX OCall sites for ORet gadgets.This setup covers the runtime entry paths examined across the evaluated libraries.

6 STEALING ENCLAVE SECRETS WITH SGXPECTRE ATTACKS

The paper demonstrates end-to-end SgxPectre attacks that read enclave registers and memory, then extract seal and attestation keys from SGX enclaves.

  • 6 STEALING ENCLAVE SECRETS WITH SGXPECTRE ATTACKS: The demonstrations target an Intel SGX SDK enclave, whose vulnerable gadgets reside in the SDK runtime libraries rather than the enclave’s own code.The authors also state that Rust-SGX is exploitable in the same way because it was developed from the official SDK.
  • 6.1 Reading Register Values: Frequent AEX events let the adversary snapshot the SSA, where enclave register values are stored during asynchronous exits.The attack can repeatedly interrupt execution and single-step trace register values.
  • 6.1 Reading Register Values: The Type-II attack maps possible byte values to monitored cache lines, using known bytes to bootstrap extraction from the SSA and other enclave memory.Four reserved zero bytes before the GPRSGX region provide a starting point for reading registers.
  • 6.1 Reading Register Values: All registers in the 184-byte GPRSGX region, including rax, rbx, rcx, rdx, r8–r15, and rip, can be read accurately.The implementation takes 414 to 3677 seconds overall, averaging 6.6 seconds per byte.
  • 6.2 Extracting Intel Secrets: Extracted seal keys enable AES-128-GCM decryption of sealed blobs outside the enclave or on another machine.The SGX hardware is no longer involved once the seal key has been exported.
  • 6.2 Extracting Intel Secrets: An extracted EPID private key enables anonymous group signatures and allows an attacker to impersonate machines or forge enclave attestation outside the enclave.The attack targets Intel’s signed quoting enclave to recover the key through its seal key.

7 COUNTERMEASURES

The evaluated microcode patch and Intel attestation-service defenses stop SgxPectre attacks on patched systems, but unpatched processors and legacy secrets remain security concerns.

  • 7 COUNTERMEASURES: IBRS restricts indirect-branch speculation, while IBPB establishes a barrier preventing earlier software from controlling later branch targets.The paper evaluates these hardware mechanisms against branch-target injection across enclave transitions and Hyper-Threading.
  • Hardware patches: After patching, experiments found no leakage during EENTER, ERESUME, or sibling-logical-core Hyper-Threading tests.Before patching, the tests observed speculative execution of secret-leaking gadgets or some secret-byte leakage.
  • Hardware patches: Patched SGX machines cleanse the BTB during EENTER and ERESUME and prevent branch injection through Hyper-Threading, rendering them immune to SgxPectre attacks.This is the paper’s conclusion from the hardware-patch tests.
  • Retpoline: Retpoline alone is ineffective on supported Skylake and Kabylake processors because depleted return-stack buffers fall back to generic BTBs.That fallback permits poisoning of return instructions.
  • Defenses by Intel’s attestation service: Intel’s attestation service rejects signatures from unpatched CPUs by reporting outdated CPUSVN, but secrets provisioned before attestation can still be leaked.The authors also warn that legacy sealed secrets may be forged using stolen seal keys.
  • Defenses by Intel’s attestation service: An extracted EPID private key can produce valid signatures for any SGX processor in the group, so GROUP_OUT_OF_DATE should be treated as completely untrusted.The authors recommend clearer messaging to ISVs.
  • Application defenses: The authors urge enclave developers to require minimum CPUSVN values and runtime developers to remove exploitable gadgets, though Type-I gadgets are difficult to eliminate.Type-II gadgets can be removed with lfence, but the performance cost requires evaluation.

8 RELATED WORK

The paper distinguishes SgxPectre from prior Spectre, Meltdown, and SGX side-channel attacks and explains why existing application defenses do not directly apply.

  • Meltdown and Spectre attacks: Spectre includes bounds-check bypass and branch-target injection, whereas Meltdown exploits out-of-order execution to access otherwise unreadable memory.The paper situates SgxPectre within these micro-architectural attack families.
  • Micro-architectural side channels in SGX: Prior SGX side channels infer secrets from secret-dependent access patterns, while SgxPectre targets memory content inside enclaves.The distinction concerns what the attacker extracts rather than the side-channel substrate alone.
  • Side-channel defenses: Existing defenses span hardware, system, and application solutions, with hardware changes effective but slow to reach commercial processors.Application defenses include compiler transformations, randomized access patterns, and static or symbolic analysis.
  • Side-channel defenses: Compiler-assisted defenses for secret-dependent flows do not apply because SgxPectre-enabling vulnerabilities are not caused by secret-dependent control or data flows.Prior static-analysis approaches model cache-side-channel vulnerabilities rather than the relevant SgxPectre patterns.

9 CONCLUSION

The paper concludes that SgxPectre extracts enclave and Intel platform secrets through systematic attack-vector, race-condition, and gadget-search techniques.

  • 9 CONCLUSION: The attacks extract seal keys, attestation keys, enclave-memory secrets, and enclave-only register values.The conclusion frames these capabilities as practical attacks against an arbitrary Intel SGX SDK enclave program.
  • 9 CONCLUSION: The study systematically explores branch-target-injection vectors, race-condition techniques, and automatic searches for code patterns needed to launch SgxPectre attacks.These techniques support the reported end-to-end demonstrations.

10 APPENDIX

Appendix Table 3 covers Type-II gadgets in Intel SGX SDK, Graphene-SGX, and Rust-SGX; [regA, regB] gadget counts are too large to include.

  • Table 3 lists [regA, regB, regC] Type-II gadgets from Intel SGX SDK, Graphene-SGX, and Rust-SGX.
  • The [regA, regB] Type-II gadget counts are too large to be included in the paper.
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