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Quantum Circuit Design for Objective Function Maximization in Gate-Model Quantum Computers
Laszlo Gyongyosi, Sandor Imre
TL;DR
The paper addresses the difficult joint problem of reducing a quantum circuit’s physical-layer resources while preserving reference-circuit behavior and maximizing a computational objective. It proposes QTAM, a simulated-annealing-based method for optimizing reduced circuit topologies under flexible hardware constraints. QTAM achieves lower reported complexity than NSGA-II in the analyzed range and is presented as applicable to arbitrary-dimensional systems and objectives.
Problem
Quantum-circuit reduction must simultaneously minimize inputs, operations, measurements, and physical layout while maximizing the objective function of the computational problem.
Source: §1 · p. 2Method
QTAM uses simulated annealing to jointly optimize physical-layer circuit structure and the computational objective under arbitrary hardware and topology constraints.
Source: §3 · p. 5, §4.2 · p. 14Results
QTAM’s maximized N_O is approximately 2 · 10^6 versus 1.25 · 10^8 for NSGA-II and approximately 2.25 · 10^6 for optimized NSGA-II, with significantly lower complexity than NSGA-II.
Source: §5 · p. 23Takeaways & Limitations
The framework provides flexible quantum-circuit design and minimization for near-term gate-model computers, with arbitrary-dimensional systems, hardware restrictions, and selected objective functions.
Source: §6 · p. 23The framework is illustrated through superconducting architectures, and one feasibility proof assumes a superconducting architecture.
Source: §1 · p. 3, §4.3.1 · p. 19
Abstract
from arXiv · showhide
Gate-model quantum computers provide an experimentally implementable architecture for near term quantum computations. To design a reduced quantum circuit that can simulate a high complexity reference quantum circuit, an optimization should be taken on the number of input quantum states, on the unitary operations of the quantum circuit, and on the number of output measurement rounds. Besides the optimization of the physical layout of the hardware layer, the quantum computer should also solve difficult computational problems very efficiently. To yield a desired output system, a particular objective function associated with the computational problem fed into the quantum computer should be maximized. The reduced gate structure should be able to produce the maximized value of the objective function. These parallel requirements must be satisfied simultaneously, which makes the optimization difficult. Here, we demonstrate a method for designing quantum circuits for gate-model quantum computers and define the Quantum Triple Annealing Minimization (QTAM) algorithm. The aim of QTAM is to determine an optimal reduced topology for the quantum circuits in the hardware layer at the maximization of the objective function of an arbitrary computational problem.
1 Introduction
The paper addresses simultaneous quantum-circuit reduction and objective-function maximization under physical-layer and hardware constraints. It introduces a gate-model design method and QTAM to find reduced topologies that preserve high-complexity circuit behavior while supporting arbitrary-dimensional systems.
1 Introduction
- QTAM simultaneously minimizes physical-layer circuit resources and maximizes an arbitrary computational problem’s objective function.The targets include circuit area, wire length, input quantum systems, and output measurements.Source: §1 · pp. 2–3
- The reduced circuit is intended to simulate an equivalent high-complexity reference circuit while producing the maximized objective value.Source: §1 · p. 2
- QTAM supports constraints on gate paths, gate organization, rounds, measurements, Hamiltonians, entanglement, and hardware restrictions such as the no-cloning theorem [26].Source: §1 · p. 2
- The framework uses generalized quantum states for arbitrary dimensions, although the examples illustrate superconducting quantum circuits and current hardware mainly uses qubits.Source: §1 · pp. 1, 3
- The paper defines a gate-model quantum-circuit design method, the QTAM algorithm, and a multilayer computational structure incorporating hardware topology restrictions.Source: §1 · p. 3
2 Related Works
Related work covers quantum optimization, circuit synthesis and optimization, simulation, fault-tolerant design, and experimental superconducting implementations. The cited studies address complementary goals such as approximate combinatorial optimization, state preparation, depth, gate count, and hardware realization.
2 Related Works
- Circuit-design research includes hierarchical permutation-circuit synthesis, low-rank stabilizer simulation, and T-count or T-depth optimization for arithmetic circuits [41] [44].Source: §2 · pp. 3–4
- Additional methods address fault-tolerant gate construction through teleportation, depth-optimal decomposition, and compilation for error correction and topological codes.Source: §2 · p. 4
- QAOA studies target approximate combinatorial optimization, near-term devices, parallel gates, varied problems, and ultrafast state preparation [21] [50] [51] [52] [53] [54].Reported examples include MaxCut, modest-depth comparisons with Goemans-Williamson [56], and GHZ preparation with O(1) circuit depth [54].Source: §2 · p. 4
- Other work demonstrates superconducting entanglement and parallel logic operations, including GHZ states with up to 10 qubits using resonator-mediated interactions.Source: §2 · p. 4
- Surveys and foundational references cover NISQ computing, computational supremacy, quantum channels, quantum-technology architectures, and logical gate-model systems [3] [19] [20] [21] [22].Source: §2 · pp. 3–4
3 System Model
QTAM jointly minimizes the physical-layer quantum circuit and maximizes a computational objective while reducing input states and measurements. Its computational model uses simulated annealing with separate temperature controls for objectives, constraints, and output-distribution closeness.
3 System Model
- QTAM simultaneously minimizes the physical-layer circuit and maximizes the objective function of an arbitrary computational problem.The method targets a reduced topology for quantum circuits in quantum-computer architectures.Source: §3 · p. 5
3.1 Computational Model
- The simulated-annealing model accepts neighboring solutions probabilistically while lowering temperature to reduce unfavorable moves and avoid local minima.The temperature follows T(t) = Tmaxexp(−R(t/k)).Source: §3.1 · p. 6
- QTAM uses separate annealing temperatures for objectives, constraints, and closeness between reduced and reference output distributions.These temperatures address the different magnitude ranges of the three function groups.Source: §3.1 · p. 6
3.2 Objective Functions
- The multiobjective formulation produces Pareto fronts that expose feasible tradeoffs among circuit performance, hardware restrictions, and optimization criteria.Secondary objectives can be combined through the single-objective function Fs.Source: §3.1 · p. 6
- Five objective functions minimize circuit area, quantum-wire area, input quantum states, and measurements while maximizing the expected computational objective value.F1 and F2 address physical layout; F3 maximizes ⟨Φ|C|Φ⟩; F4 and F5 reduce input size and measurement count.Source: §3.2 · pp. 6–7
3.3 Constraint Violations
QTAM modifies Pareto dominance using distribution-closeness and constraint-violation measures before applying objective dominance. This prioritizes reduced circuits that are closer to feasibility and reproduce the reference circuit’s output distribution.
3.3 Constraint Violations
- QTAM modifies Pareto dominance with constraint violations and distribution closeness to support feasible hardware-aware tradeoffs.The optimization uses three constraint-violation values within its multiobjective search.Source: §3.3 · p. 7, §3.3.1 · p. 8
3.3.1 Distribution Closeness Dominance
- Distribution-closeness dominance compares the reduced circuit’s output distribution with the reference circuit using relative entropy.The distributions are measured after the reference circuit’s M-measurement phase and the reduced circuit’s corresponding output.Source: §3.3.1 · p. 8
- A solution dominates another under distribution closeness when both are infeasible but one is closer to feasibility, or when it is feasible and the other is not.The comparison uses summed distribution-closeness violation values.Source: §3.3.1 · p. 8
3.3.2 Constraint Dominance
- Constraint dominance applies the same feasibility ordering to summed constraint-violation values.It favors feasible solutions over infeasible ones and compares infeasible solutions by their violation sums.Source: §3.3.2 · pp. 8–9
3.3.3 Objective Dominance
- Objective dominance uses all five objectives and requires no worse performance on every objective plus strict improvement on at least one.Objective ranges are incorporated through the dominance function.Source: §3.3.3 · p. 9
3.4 Objective Function Maximization
The objective-maximization formulation represents computational problems through parameterized unitary operations and seeks parameters that maximize the expected objective value. The construction supports quantum systems of arbitrary dimension while specializing to qubits when d = 2.
3.4 Objective Function Maximization
- For a qubit system, the Hilbert-space dimension is 2^n and the initial state is the uniform superposition over computational-basis states.More generally, d is the dimension of each quantum system and n is the number of quantum states.Source: §3.4 · pp. 9–10
- The objective-maximization problem seeks a parameter string z that maximizes the computational objective for an n-bit problem with m constraints.Constraint satisfaction is encoded by Cα(z) = 1 when constraint α is satisfied and 0 otherwise.Source: §3.4 · pp. 9–10
- Parameterized single-port and connected-port unitary operations define the multilayer quantum-gate circuit.The parameters γ and µ can be restricted to [0, π] because the relevant operator eigenvalues are ±1.Source: §3.4 · p. 10
- The quantum circuit applies collections of parameterized unitaries to an initial state, producing a system state whose objective value is optimized.The maximization is formulated as finding parameter sets for the circuit state.Source: §3.4 · pp. 10–11
3.5 The QTAM Algorithm
QTAM combines Pareto-based archive management with triple annealing over objective, constraint, and distribution-closeness dominance. Its stated computational complexity is O(NdNit |P| (Nobj + log2(|P|))).
3.5 The QTAM Algorithm
- QTAM uses three annealing temperatures to evaluate acceptance probabilities for objectives, constraints, and distribution closeness.The algorithm defines Tf(t), Tg(t), and Tc(t) for these respective components.Source: §3.5 · p. 11
- Archive updates retain nondominated candidates, remove dominated points, and select the best As elements by crowding distance when capacity is exceeded.Different dominance cases invoke the corresponding archive sub-procedures.Source: §3.5 · p. 11, §3.5.1 · pp. 13–14
3.5.1 Computational Complexity of QTAM
- O(NdNit |P| (Nobj + log2 (|P|))) is the stated computational complexity of QTAM.Nd is the number of dominance measures, |P| the population size, and Nobj the number of objectives.Source: §3.5.1 · p. 11
3.5 The QTAM Algorithm
- Each iteration perturbs an archived solution, evaluates constrained Pareto dominance, and computes acceptance probabilities for the candidate.The archive retains solutions using crowding distance and dominance relations.Source: §3.5.1 · p. 12
- QTAM repeats its update and acceptance steps until the total iteration count Nit is reached.Nit denotes the total number of iterations.Source: §3.5.1 · pp. 11, 13
4 Wiring Optimization and Objective Function Maximization
This section presents methods for optimizing multilayer quantum-circuit wiring and objective-function maximization under gate-model hardware constraints. It develops connectivity procedures, including shortest-path construction between quantum-gate ports, for designing the resulting topology.
4.1 Multilayer Quantum Circuit Grid
- The multilayer circuit grid represents gates and ports across r layers, with hardware restrictions requiring gates to operate in several rounds.Gate-to-gate connectivity is represented through a directed graph whose vertices are quantum ports and whose edges carry connection costs.Source: §4.1 · p. 14, §4.3.2 · p. 20
4.2 Method
- Method 1 simultaneously minimizes physical-layer wiring and maximizes the objective function, reducing quantum-wire count while achieving the desired system state.The procedure realizes F2 ∧ F3 by minimizing wiring lengths and Hamiltonian energy while maximizing the computational objective.Source: §4.2 · pp. 14–15
4.3 Quantum Circuit Minimization
- Method 1 selects separation points and connection topologies that minimize path costs while maximizing overlapped paths and the associated objective function.For candidate assignments, the method evaluates objective functions and selects the solution yielding the maximized value C∗.Source: §4.3 · pp. 16–17
4.3.1 Quantum Wire Area Minimization
- Objective function F2 minimizes total quantum-wire area by reducing long port-to-port connections across circuit nets, and its feasibility is established for multilayer circuits.The implementation assigns condensate amplitudes, constructs a residual network, enforces strong connectivity, and outputs a topology minimizing wQG.Source: §4.3.1 · pp. 19–20
4.3.2 Processing in the Multilayer Structure
- Multilayer processing computes port distances, weights nonzero wire lengths, and uses Kruskal’s algorithm to obtain a minimum spanning tree for connectivity.The procedure assumes a quantum system cannot participate in more than one quantum gate at a particular time.Source: §4.3.2 · pp. 20–21
- The multilayer processing repeatedly adds STQG quantum wires to the MQG multilayer topological map for all QG circuit nets.The procedure repeats steps 4–6 until the MQG structure is no longer strongly connected.Source: §4.3.2 · p. 21
- The multilayer QG structure uses layers and two-dimensional coordinates for quantum ports, with port distances measured by Manhattan distance d_L1((j,k),(m,o)) = |m − j| + |o − k|.The structure contains r layers l_z and dimension k = 2 in each layer.Source: §4.3.2 · p. 21
Algorithm
- The Quantum Shortest Path Algorithm finds shortest paths in a multilayer QG quantum-circuit structure using steps for shortest-path determination between quantum-gate ports.Its complexity is inherited from the A* search method because the algorithm is based on A* search.Source: Algorithm · p. 21
5 Performance Evaluation
Performance evaluation compares QTAM with NSGA-II and optimized NSGA-II using iteration complexity, while the accompanying procedures allocate ports and find low-cost paths in multilayer quantum circuits.
5 Performance Evaluation
- QTAM complexity is compared against NSGA-II and optimized NSGA-II through the number of iterations, with each method represented in a separate panel of Fig. 4.The reported comparison considers both the standard and optimized NSGA-II situations.Source: §5 · pp. 21, 23
Quantum Circuit Port Allocation
- Port allocation and shortest-path construction are illustrated for the Gk,r multilayer structure, where the objective is to connect gate ports under physical-layer restrictions.The figures present wiring and port-allocation procedures rather than numerical performance outcomes.Source: Figure 3 · p. 22, §5 · p. 23
- The multilayer path problem accounts for gates applied in separate rounds, blocked or unavailable ports, and auxiliary grid vertices with degree at most 8.These hardware constraints determine which ports can be connected and how paths are evaluated.Source: §5 · p. 22
Quantum Shortest Path Algorithm
- The Quantum Shortest Path Algorithm determines lowest-cost paths between quantum-gate ports in a multilayer grid using blockage and port information.Its cost function incorporates real path size and L1 grid distance before parallel A* search identifies the path P*(x, y).Source: §5 · p. 23
5 Performance Evaluation
- 2 · 10^6 iterations for QTAM versus 1.25 · 10^8 for NSGA-II, while optimized NSGA-II reaches 2.25 · 10^6; QTAM is significantly lower than NSGA-II without nondominated-procedure optimization.The comparison uses Nobj = 5 for NSGA-II and Nd = 3 for QTAM.Source: §5 · p. 23
6 Conclusions
The paper presents a flexible framework for near-term gate-model quantum circuit design and applies it to arbitrary-dimensional systems, hardware restrictions, input constraints, and objective functions. Figure 4 compares the computational complexity of QTAM with NSGA-II variants across iteration counts and population sizes.
6 Conclusions
- The framework supports quantum circuit design for near-term gate-model computers with arbitrary-dimensional systems, hardware restrictions, input constraints, and objective functions.These features allow the scheme to accommodate experimental development constraints and different computational problems.Source: §6 · p. 23
- Figure 4 compares the number of operations for QTAM, NSGA-II, and optimized NSGA-II as Nit and |P| vary.The figure covers Nit from 1 to 100 and |P| from 1 to 500.Source: Figure 4 · p. 24
A.1 Abbreviations
The abbreviations appendix expands the principal names used in the paper, including the proposed QTAM method and related quantum, optimization, and hardware terms.
A.1 Abbreviations
- QSPA denotes Quantum Shortest Path Algorithm, while EDA and VLSI denote Electronic Design Automation and Very-Large-Scale Integration.Source: §A.1 · p. 29
- QTAM denotes Quantum Triple Annealing Minimization, the paper’s proposed method.Source: §A.1 · p. 29
A.2 Notations
The notation appendix defines symbols for the quantum circuit structure, optimization objectives, constraints, paths, networks, and algorithmic quantities used throughout the paper.
A.2 Notations
- Optimization notation includes design variables, weight vectors, objective and constraint dominance functions, objective ranges, and Pareto-dominance checking.These symbols describe the multiobjective optimization procedure and its violation measures.Source: §A.2 · p. 30
- Circuit geometry is represented through gates, ports, layers, cells, wires, area, height, depth, and wire-area quantities.The appendix also defines wire lengths, effective widths, grid coordinates, and quantum circuit dimensions.Source: §A.2 · p. 30
- The notation covers quantum-system states, parameterized unitaries, measurements, objective functions, and maximized objectives.Examples include |⃗Φ⟩, U, m, C(z), and C∗(z).Source: §A.2 · pp. 30–31
- Algorithmic quantities include iterations, dominance measures, objectives, random solutions, moving parameters, and constraint or distribution-closeness violations.The notation explicitly defines Nit, Nd, Nobj, ξ, ν, and associated violation counts and sums.Source: §A.2 · pp. 30–31
- Network and routing notation describes residual networks, topological maps, connection lists, negative cycles, subnets, Bellman-Ford processing, spanning trees, and manufacturable wire widths.Path costs combine real path size with L1 distance, and P∗(x,y) denotes a lowest-cost path.Source: §A.2 · p. 33