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A 0.086-mm$^2$ 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28nm CMOS

Charlotte Frenkel, Martin Lefebvre, Jean-Didier Legat, David Bol

arXiv:1804.07858v3cs.ET

TL;DR

Online learning is difficult to embed in compact, versatile SNN processors because of its complexity and area overhead, yet it is important for adaptation with limited on-the-fly data. The paper presents ODIN, a 28nm FDSOI digital processor combining dense SDSP synapses with configurable LIF or phenomenological neurons. ODIN reaches 12.7pJ/SOP and supports single-presentation online MNIST learning with 84.5% accuracy at 15nJ/inference.

  • Problem

    Embedded online learning remains difficult for compact, versatile SNNs, although it is needed for real-time adaptation to new features in uncontrolled environments with limited training data.

  • Method

    ODIN uses a 28nm FDSOI digital SNN processor with time-multiplexed online-learning synapses, configurable neuron models, and AER event processing.

  • Results

    12.7pJ/SOP was measured at 0.55V, while single-presentation online SDSP training on 6k MNIST samples reached 84.5% accuracy and 15nJ/inference.

  • Takeaways & Limitations

    ODIN demonstrates a compact digital platform for embedded online learning, dense synapse integration, versatile neuron behavior, and low-energy spiking inference.

  • Takeaways & Limitations

    ODIN is a single neurosynaptic core whose large-scale integration requires external routing tables; hierarchical event-routing infrastructure remains future work.

Abstract

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Shifting computing architectures from von Neumann to event-based spiking neural networks (SNNs) uncovers new opportunities for low-power processing of sensory data in applications such as vision or sensorimotor control. Exploring roads toward cognitive SNNs requires the design of compact, low-power and versatile experimentation platforms with the key requirement of online learning in order to adapt and learn new features in uncontrolled environments. However, embedding online learning in SNNs is currently hindered by high incurred complexity and area overheads. In this work, we present ODIN, a 0.086-mm$^2$ 64k-synapse 256-neuron online-learning digital spiking neuromorphic processor in 28nm FDSOI CMOS achieving a minimum energy per synaptic operation (SOP) of 12.7pJ. It leverages an efficient implementation of the spike-driven synaptic plasticity (SDSP) learning rule for high-density embedded online learning with only 0.68$μ$m$^2$ per 4-bit synapse. Neurons can be independently configured as a standard leaky integrate-and-fire (LIF) model or as a custom phenomenological model that emulates the 20 Izhikevich behaviors found in biological spiking neurons. Using a single presentation of 6k 16$\times$16 MNIST training images to a single-layer fully-connected 10-neuron network with on-chip SDSP-based learning, ODIN achieves a classification accuracy of 84.5% while consuming only 15nJ/inference at 0.55V using rank order coding. ODIN thus enables further developments toward cognitive neuromorphic devices for low-power, adaptive and low-cost processing.

I. INTRODUCTION

Neuromorphic systems pursue event-based, brain-inspired processing for power- and resource-constrained applications, but versatile digital SNNs still face high complexity and embedded online-learning overheads.

  • Motivation: Brain-inspired event-driven processing targets autonomous sensors, sensorimotor systems, brain-machine interfaces, and neuroscience platforms under stringent power constraints.Biological systems motivate a paradigm shift toward sparse event-based computation for distributed and embedded applications.
  • Related approaches: Digital SNN implementations offer shorter design cycles and lower sensitivity to noise, PVT variations, and mismatch than many analog approaches.The paper positions digital designs as a route toward technology-scalable neuromorphic systems.
  • Motivation: Online learning is needed for real-time adaptation when new features arrive on-the-fly in uncontrolled environments with limited training data.The passage contrasts this setting with offline backpropagation-based training, which relies on repeated presentations of extensive datasets.
  • Challenges: Resource-efficient digital SNNs remain challenging because emulating brain dynamics requires complex neuron and synapse models.The introduction identifies biophysical accuracy and model versatility as open implementation challenges.

II. ARCHITECTURE AND IMPLEMENTATION

ODIN uses a time-multiplexed digital crossbar in which SRAM-stored neuron and synapse states are sequentially updated, with AER events controlling configurable operations across 256 neurons and 64k synapses.

  • Crossbar architecture: The time-multiplexed crossbar stores N neuron states and N^2 synapse states in SRAM while a controller sequentially emulates an N×N online-learning crossbar.Sequential updates reduce silicon area by leveraging high-speed digital logic.
  • Event interfaces: The input AER interface supports neuron spike, single-synapse, virtual synapse, and time-reference events through encoded address fields.These event types provide distinct controls for network updates, individual synapses, fixed-weight inputs, and timing.
  • Processor organization: ODIN implements the architecture for N=256 using 4kB neuron SRAM, 32kB synapse SRAM, a global time-multiplexing controller, SPI configuration, and AER event interfaces.The scheduler also arbitrates external and internally generated events.
  • Timing: Each SOP takes two clock cycles, retrieving a destination neuron state and synaptic weight before writing back the updated neuron state.Synapse memory accesses handle eight 4-bit synapses at a time because the SRAM uses 32-bit words.

A. Synapse array

ODIN embeds SDSP online learning in every synapse using a time-multiplexed digital implementation compatible with standard foundry SRAMs and a compact 4-bit synapse structure.

  • Learning rule: SDSP updates synapses whenever a presynaptic spike occurs, using the destination neuron's membrane potential and Calcium state rather than relative pre- and postsynaptic spike times.This contrasts with STDP, which depends on t_pre and t_post.
  • Synapse structure: Each synapse combines a 3-bit weight with a 1-bit mapping-table flag that locally enables or disables online learning.Neuron-specific SDSP thresholds are individually programmable through SPI.
  • Implementation: 0.68µm^2 per 4-bit synapse includes synapse SRAM, SDSP update logic, and the added neuronal Calcium variable for embedded online learning.The implementation achieves high density while incorporating local plasticity.
  • Memory compatibility: The time-multiplexed SDSP rule works with standard single-port foundry SRAMs, unlike the cited probabilistic STDP design requiring custom dual-port SRAM access.Standard SRAM compatibility avoids custom-memory design overheads and supports foundry implementation flows.

B. Neuron array

ODIN combines individually selectable LIF and phenomenological neurons with event-driven dynamics and a rotating-FIFO scheduler that supports the 20 Izhikevich behaviors and burst timing.

  • Neuron models: Each of ODIN's 256 neurons independently selects either an 8-bit LIF model or a phenomenological model emulating 20 Izhikevich behaviors.Both models include a 3-bit Calcium variable and thresholds for SDSP online learning.
  • Phenomenological neuron: The phenomenological neuron uses three stages corresponding to dendrites, soma, and axon, with configurable subthreshold dynamics and burst generation.Its four combinational blocks capture the functionalities needed to describe the 20 Izhikevich behaviors.
  • Neuron configuration: 126 parameter and state bits per neuron configure model selection, neuron state, and the 70-bit phenomenological parameter array.Parameters and initial states are preloaded through SPI.
  • Input processing: An 11-bit accumulator controls effective fan-in, while presynaptic addresses can designate excitatory or inhibitory inputs and time-reference events apply configurable leakage.This supports primitives such as winner-take-all networks.
  • Event scheduling: The scheduler decodes burst packets into single-spike events distributed across rotating four-stage FIFOs to reproduce specified inter-spike intervals.Event packets encode source address, spike count, and ISI, while FIFO priorities arbitrate event timing.

C. Scheduler

ODIN’s scheduler arbitrates external and internally generated spiking events using prioritized FIFO structures, while burst events are decomposed into timestep-separated single spikes.

  • C. Scheduler: The scheduler arbitrates spiking and bursting events from all neurons together with external and internally generated neuron events.Spiking and bursting neurons send 14-bit event packets to the scheduler.
  • C. Scheduler: Single-spike events receive the highest priority and are handled as soon as they become available.
  • C. Scheduler: Burst packets are split into single-spike events across rotating four-stage FIFOs representing successive timesteps.The scheduler uses a configurable local timestep to generate burst inter-spike intervals.

III. SPECIFICATIONS, MEASUREMENTS AND BENCHMARKING RESULTS

ODIN was fabricated in 28-nm FDSOI CMOS and occupies a compact 320µm×270µm processor area, with the remaining chip area assigned to unrelated blocks.

  • III. SPECIFICATIONS, MEASUREMENTS AND BENCHMARKING RESULTS: ODIN uses a 28-nm fully depleted silicon-on-insulator CMOS process and a fully synthesizable synchronous digital implementation flow.
  • III. SPECIFICATIONS, MEASUREMENTS AND BENCHMARKING RESULTS: 320µm×270µm is the post-shrink area occupied by the ODIN neuromorphic processor.The chip microphotograph and floorplan identify unrelated blocks outside this processor area.
  • III. SPECIFICATIONS, MEASUREMENTS AND BENCHMARKING RESULTS: Fig. 8 summarizes ODIN specifications and measurements while identifying Pleak, Pidle, and ESOP as parameters of its power model.

A. Chip specifications and measurements

ODIN’s measured energy depends on whether incremental or total SOP energy is reported and on operating time scale. At 0.55V, total energy per SOP is 12.7pJ in accelerated time and 54pJ at biological time.

  • A. Chip specifications and measurements: 8.43pJ is ODIN’s incremental energy per SOP ESOP at 0.55V after subtracting leakage and idle power.The measurement saturates the scheduler with neuron spike events, each producing 256 SOPs.
  • A. Chip specifications and measurements: Etot,SOP divides whole-chip power P by SOP rate rSOP, whereas ESOP excludes leakage and idle contributions.The total definition is described as more application-driven and representative of real energy-per-SOP performance.
  • A. Chip specifications and measurements: 12.7pJ is the global energy per SOP Etot,SOP at 0.55V, 75MHz, and the maximum rate of 37.5MSOP/s.Leakage contributes 6% and idle power 28% of total power in this accelerated-time condition.
  • A. Chip specifications and measurements: 54pJ is the global energy per SOP Etot,SOP at biological time, where leakage accounts for 78% of total power.The estimate assumes all 256 neurons spike at 10Hz, yielding 650kSOP/s and requiring at least 1.3MHz.

B. Neuron and synapse characterization

Silicon measurements validate ODIN’s phenomenological neuron behaviors and the stochastic SDSP learning mechanism under controlled stimulation conditions.

  • B. Neuron and synapse characterization: Twenty Izhikevich behaviors are validated in silicon with output spikes and membrane dynamics matching the original behaviors’ 20ms time references.
  • B. Neuron and synapse characterization: Identical Poisson statistics can produce either no LTP or an LTP transition after 200ms in the SDSP mechanism.The presynaptic and postsynaptic rates are 70Hz and 40Hz, respectively.
  • B. Neuron and synapse characterization: The MNIST benchmark compares on-chip online SDSP learning with off-chip offline learning setups for a 10-neuron LIF-based network.

C. Comparison of online SDSP- and offline gradient-based supervised learning for spiking neural networks in ODIN

ODIN compares embedded online SDSP learning with off-chip offline SGD, exposing a tradeoff between training data, accuracy, and inference energy. Online learning reaches competitive accuracy with a single presentation, while offline SGD achieves higher accuracy using substantially more training.

  • Learning-strategy selection: ODIN can select online SDSP or offline gradient-based learning per application because synapses can be individually configured as plastic or static.The mapping table enables local learning control in each synapse.
  • Online SDSP learning: 85% accuracy saturates for online SDSP training with 6k or more MNIST samples, even when samples are presented only once.At 0.55V, online learning consumes 105nJ/sample, including 95nJ from the teacher signal and 10nJ from the input character.
  • Offline gradient-based learning: 91.9% accuracy is reached with offline SGD using all 60k MNIST training samples over 100 epochs.The theoretical pre-upload Keras accuracy is 92.5%.
  • Inference tradeoffs: 15nJ/inference yields 84.5% accuracy with rank order coding after on-chip learning, compared with 404nJ/inference and 85% using rate coding.Rank order inference stops after one output spike, whereas rate coding requires longer presentations to accumulate sufficient statistics.
  • Inference tradeoffs: 451nJ/inference yields 91.9% accuracy after off-chip learning with rate coding, while rank order coding reaches 91.4% accuracy after off-chip learning at 15nJ/inference.The coding scheme therefore changes the accuracy–energy operating point for both learned-weight strategies.
  • Scope and extensions: More neuron resources and complex network topologies could increase MNIST accuracy, while deeper gradient-based networks require offline-trained weights mapped into ODIN.The paper identifies two-layer reservoirs, unsupervised WTA networks, and ANN-to-SNN conversion as future or alternative paths.

IV. DISCUSSION

ODIN combines dense online-learning synapses with versatile neurons in a compact digital neurosynaptic core. It compares favorably with prior chips in density and energy, while its current scope excludes hierarchical large-scale routing.

  • ODIN currently provides a single neurosynaptic core using standard AER interfaces, with external routing tables required for inter-chip connectivity.Hierarchical event-routing infrastructure for efficient large-scale integration is left for future work.
  • ODIN matches TrueNorth’s 256-neuron, 64k-synapse neurosynaptic core in 28nm CMOS while adding online learning and quadrupling synapse bits with slightly lower area.The comparison directly targets density because the two chips have identical neuron and synapse counts and technology node.
  • 12.7pJ per SOP is ODIN’s minimum global energy at 0.55V and maximum SOP rate.Reported SOP energies across chips are not directly comparable because measurement processes are not standardized.

V. CONCLUSION

The paper presents ODIN as a compact digital SNN processor with dense embedded online learning and versatile neuron models. It demonstrates low-energy MNIST classification with both online and offline training modes.

  • 0.086mm2 integrates 256 neurons and 64k synapses in ODIN’s 28nm FDSOI CMOS processor.Each 4-bit synapse occupies 0.68µm2 and embeds SDSP online learning.
  • 20 Izhikevich behaviors are emulated alongside independently configurable LIF or phenomenological neuron models.The SDSP learning rule includes an overfitting-prevention mechanism.
  • 84.5% MNIST accuracy is achieved with single-presentation on-chip SDSP learning, while inference consumes 15nJ per classification.The experiment uses a single-layer network and targets power- and resource-constrained training.
  • 91.4% MNIST accuracy is achieved with offline training while retaining 15nJ per classification during inference.Offline learning is presented for applications without stringent training-phase power or resource constraints.
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