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Memristor Crossbars with 4.5 Terabits-per-Inch-Square Density and Two Nanometer Dimension
Shuang Pi, Can Li, Hao Jiang, Weiwei Xia, Huolin Xin, J. Joshua Yang, Qiangfei Xia
TL;DR
High-density memristor crossbars are needed for nonvolatile memory and bio-inspired computing, but dense ordered arrays face scaling, crosstalk, and circuit-adoption challenges. The paper demonstrates functional 2 × 2 nm memristor crossbars, including 4.5 Tbit/inch^2 packing density and low-current operation.
Problem
High-density crossbar arrays are challenging because nanoscale scaling, dense ordered electrode integration, and write/read-current crosstalk constrain operational circuits.
Method
The paper explores extreme memristor scaling by constructing functional crossbar arrays using nanofin electrodes and self-rectifying 2 nm memristors.
Results
4.5 Tbit/inch^2 packing density, ~0.1 nm thickness control, and 46 nA operational current with 0.23 µW peak programming power were reported.
Takeaways & Limitations
The demonstrated densely packed crossbars provide extremely small working devices for high-density information storage and processing.
Takeaways & Limitations
The arrays’ suitability for fully random-access operation has not been demonstrated, and nanoscale dimensions remain a barrier to adoption in operational circuits.
Abstract
from arXiv · showhide
Memristor is a promising building block for the next generation nonvolatile random access memory and bio-inspired computing systems. Organizing memristors into high density crossbar arrays, although challenging, is critical to meet the ever-growing high capacity and low energy demands of these applications especially in the big data era. Here, we construct memristor crossbars with a single-layer density up to 4.5 terabits per inch square, an order of magnitude denser than the state- of-the-art 64-layer triple level cell NAND flash technology. The memristors in the crossbars are 2 $\times$ 2 nm$^2$ in size, capable of switching with tens of nano ampere electric current. The densely packed memristor crossbars of extremely small working devices provides a power-efficient solution for high density information storage and processing.
1 Department of Electrical and Computer Engineering, University of Massachusetts, Amherst,
The paper develops nanofin electrodes to overcome nanoscale resistance and crossbar crosstalk, enabling experimentally demonstrated 2 × 2 nm2 memristors at 4.5 Tbit/inch2 density. These devices switch independently with low current and power, supporting dense memory and unconventional computing.
- Nanofin electrode engineering: Ultrathin platinum nanofins provide continuous, low-resistance electrodes with 100% fabrication yield and scalability below the demonstrated 2 nm dimension.The nanofins reach 2 nm thickness, remain continuous into the sub-1 nm domain, and can be fabricated down to a 1 nm domain.
- Nanofin electrode engineering: Nanofin electrodes combine high conductivity with isolation, exhibiting less than 1 pA leakage between neighboring fins and an average wire resistance of 470 Ω/µm.Measured resistances for 200, 440, and 680 µm nanofins were 338, 175, and 108 × 103 Ω, respectively.
- Memristor operation: The 2 nm memristors switch nonvolatilely between 0.14 GΩ ON and 63.6 GΩ OFF states, with programming current below 50 nA and peak power of 230 nW.Their self-rectifying behavior has an average rectifying ratio of 1.06 × 103, reducing the need for external selector devices.
- Crosstalk and scalability: Electric-field and thermal simulations indicate negligible crosstalk: neighboring-cell fields fall nearly one order lower, while unselected-cell temperature rises by less than 1 K.The selected-cell switching center remains near ambient temperature at 301 K.
- Crossbar fabrication and density: 2 × 2 nm2 memristors at 4.5 Tbit/inch2 packing density were experimentally constructed in functional crossbar arrays.The array uses a 12 nm pitch and is reported as the first of its kind at this scale.
Methods
The methods fabricate vertically structured nanofin crossbars, integrate oxide-based memristor layers, and prepare devices for electrical and TEM characterization.
- Substrate preparation: Rectangular trenches were formed in silicon and processed with thermal oxidation, oxide removal, and sidewall passivation.The trenches were approximately 680 µm long, 70 µm wide, and 5 µm deep.
- Nanofins formation: Ge and Pt films were obliquely evaporated onto vertical SiO2 sidewalls to form nanofins, followed by Cu contact fabrication.The Ge and Pt films were each 2 nm thick, while the Cu contacts were 180 nm thick.
- Nanofins formation: Photolithography, magnetron sputtering, liftoff, and ALD were used to construct repeated nanofin layers with Al2O3 insulation.A 5.5 nm Al2O3 layer was deposited by ALD at 250 °C.
- Memristor crossbar fabrication: Ti was oxidized to TiOx, HfO2 was deposited on top, and two nanofin chips were aligned and directly bonded to complete the crossbar.The Ti layer was approximately 2 nm thick and the HfO2 layer approximately 4 nm thick.
- Electrical measurements: Reactive ion etching opened access windows to the Cu pads, after which I-V characterization was performed with a semiconductor parameter analyzer.The access windows measured 40 µm by 40 µm.
- TEM imaging: Crossbar structures were extracted by focused ion beam, mounted on Cu grids, aligned to the ion beam, and thinned to approximately 90 nm for TEM imaging.The bonding interface was aligned approximately parallel with the ion beam before further thinning.
6. Sheridan, P. M. et al. Sparse coding with memristor networks. Nature Nanotech. 12, 784–789
This section contains a bibliographic citation for work on sparse coding with memristor networks.
- Related work: The reference is listed among prior work related to memristor-based computing.Only bibliographic information is supplied in the passage.
8. Wang, Z., et al, Memristor with diffusive dynamics as synaptic emulators for neuromorphic
This section lists prior publications on memristor devices, crossbars, nanoscale structures, and related computing technologies.
- Related work: The cited literature includes memristor-based analog computation, neural-network classification, and analog signal and image processing.These topics appear in the titles of the listed prior works.
- Related work: Prior studies reported Hf/HfOx crossbar resistive RAM and 8 nm × 8 nm memristive cross-point arrays.The cited devices are associated with low-energy operation and nanoimprint lithography, respectively.
- Related work: The references cover sub-5 nm sidewall electrodes, graphene-edge electrodes, and scalability of valence-change memory.These works address nanoscale electrode or device scaling topics.
- Related work: Additional citations address nanowires, carbon nanotubes, graphene nanomeshes, and directed assembly of one-dimensional nanostructures.The listed publications span nanoscale materials and network fabrication.
- Related work: The section also cites work on highly aligned nanowires, molecular electronic memory, and nanoscale nanowire lattices and circuits.These references concern high-density nanoscale structures or memory.
21. Abbas, A. N. et al. Patterning, characterization, and chemical sensing applications of graphene
This section lists related work on nanoscale materials, resistive-memory arrays, switching mechanisms, and semiconductor technology scaling.
- Related work: Prior work addresses ultrahigh-density nanowire lattices and circuits and the conductivity of thin metallic films.The cited topics span nanoscale circuit structures and metallic transport.
- Related work: The cited literature discusses electron mean free paths, sub-10 nm cross-point memory scaling, and carbon nanotubes as quantum wires.These works relate nanoscale transport and interconnect constraints to memory scaling.
- Related work: Additional references cover nonlinear memristors, thermal crosstalk in three-dimensional RRAM arrays, and low-power bipolar TMO ReRAM.These titles identify circuit-level and operating considerations for resistive memory.
- Related work: The section also cites ribbon-like memristive junctions, semiconductor roadmaps, and metal-oxide memristor switching mechanisms.The references include a patent, the 2015 ITRS edition, and studies of nanoscale conduction channels.