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Read Disturb Errors in MLC NAND Flash Memory

Yu Cai, Yixin Luo, Saugata Ghose, Erich F. Haratsch, Ken Mai, Onur Mutlu

arXiv:1805.03283v1cs.AR

TL;DR

Read disturb errors are an increasingly important reliability concern in scaled MLC NAND flash, but have been understudied in modern devices. This paper experimentally characterizes the phenomenon in commercial 2Y-nm chips and develops mitigation and recovery mechanisms, with Vpass Tuning extending flash lifetime by 21%.

  • Problem

    Read disturb errors threaten the reliability of scaled MLC NAND flash, yet modern devices had been understudied as their susceptibility increased with technology scaling.

  • Method

    The paper experimentally characterizes read disturb in commercial 2Y-nm MLC NAND chips and uses the findings to tune Vpass per block and probabilistically correct disturb-prone cells.

  • Results

    Vpass Tuning extends flash lifetime by 21% using real workload traces, while the characterization finds greater read-disturb impact with more neighboring-page reads and program/erase cycles.

  • Takeaways & Limitations

    Reducing pass-through voltage can mitigate read disturb, and characterizing the phenomenon supports additional error mitigation and tolerance mechanisms as flash scaling continues.

  • Takeaways & Limitations

    Commercial flash devices lack an interface for directly changing Vpass, so experiments mimic Vpass changes through read-retry adjustments to Vref on one wordline per block across ten blocks.

Abstract

from arXiv · show

This paper summarizes our work on experimentally characterizing, mitigating, and recovering read disturb errors in multi-level cell (MLC) NAND flash memory, which was published in DSN 2015, and examines the work's significance and future potential. NAND flash memory reliability continues to degrade as the memory is scaled down and more bits are programmed per cell. A key contributor to this reduced reliability is read disturb, where a read to one row of cells impacts the threshold voltages of unread flash cells in different rows of the same block. For the first time in open literature, this work experimentally characterizes read disturb errors on state-of-the-art 2Y-nm (i.e., 20-24 nm) MLC NAND flash memory chips. Our findings (1) correlate the magnitude of threshold voltage shifts with read operation counts, (2) demonstrate how program/erase cycle count and retention age affect the read-disturb-induced error rate, and (3) identify that lowering pass-through voltage levels reduces the impact of read disturb and extend flash lifetime. Particularly, we find that the probability of read disturb errors increases with both higher wear-out and higher pass-through voltage levels. We leverage these findings to develop two new techniques. The first technique mitigates read disturb errors by dynamically tuning the pass-through voltage on a per-block basis. Using real workload traces, our evaluations show that this technique increases flash memory endurance by an average of 21%. The second technique recovers from previously-uncorrectable flash errors by identifying and probabilistically correcting cells susceptible to read disturb errors. Our evaluations show that this recovery technique reduces the raw bit error rate by 36%.

1. Introduction

The paper experimentally characterizes read disturb in state-of-the-art 2Y-nm MLC NAND flash and develops mechanisms to reduce its reliability impact. It links disturb effects to flash operating conditions and uses those findings for per-block voltage tuning and probabilistic recovery.

  • Motivation: Read disturb was previously understudied in MLC NAND, with no open-literature characterization before this work.Modern MLC devices can experience read-disturb errors after as few as 20,000 reads, compared with 100,000 reads in first-generation MLC devices.
  • Mechanism: Read operations can shift unread cells to higher threshold voltages and move them into a different logical state.Unread cells share bitlines with the cell being read and are powered by a pass-through voltage, producing an increased tunneling effect during reads.
  • Characterization findings: Read-disturb effects increase with neighboring-page reads and program/erase cycles, while lower-threshold-voltage cells are more susceptible.The characterization was performed on commercial 2Y-nm, or 20-24 nm, MLC NAND flash chips.
  • Characterization findings: Lowering pass-through voltage reduces the effect of each read, but can increase read errors by reducing the ability of values to pass through unread cells.The findings expose a trade-off between mitigating read disturb and preserving read functionality.
  • Mitigation: Vpass Tuning extends flash lifetime by 21% by finding the lowest per-block pass-through voltage that retains data correctness.The evaluation uses real workload traces and dynamically tunes pass-through voltage on a per-block basis.
  • Recovery: Read Disturb Recovery reduces raw bit error rate by 36% by probabilistically correcting cells susceptible to read disturb.The mechanism exploits differences in cell susceptibility to extend the effective correction capability of error-correcting codes.

2. Characterizing Read Disturb in Real NAND Flash Memory Chips

Experiments on commercial 2Y-nm MLC NAND flash chips quantify how read disturb shifts threshold voltages and increases raw bit error rates. They also show that relaxing Vpass reduces read-disturb errors but introduces a trade-off with bitline propagation errors, which varies with retention age.

  • Experimental methodology: The FPGA-based platform uses read-retry to measure normalized threshold voltages, while Vpass effects are mimicked by changing Vref on one wordline per block.Experiments repeat measurements over ten blocks because commercial chips provide no direct interface for altering Vpass.
  • Read-disturb perturbations: Threshold-voltage shifts increase with read-disturb operations and are larger for cells with lower initial threshold voltages.Unread cells are measured after 0, 250K, 500K, and 1 million reads to other cells in the same block.
  • Error-rate effects: Raw bit error rate increases roughly linearly with read-disturb operations, and read-disturb effects are greater after more P/E cycles.Figure 3 compares RBER across increasing read-disturb counts and different amounts of wear.
  • Pass-through voltage impact: At 100K reads, lowering Vpass by 2% can reduce RBER by as much as 50%.For a fixed RBER, decreasing Vpass exponentially increases the number of tolerable read disturbs.
  • Pass-through voltage trade-off: Relaxing Vpass can reduce read disturb but may cause bitline propagation errors when unread cells incorrectly remain off.These propagation errors do not alter the flash cell’s threshold voltage.
  • Retention-age effects: For a fixed relaxed Vpass, additional read-error rate is lower at longer retention ages because retention loss lowers cell threshold voltages.Across studied retention ages, Vpass can first be lowered without inducing read errors; greater relaxation increases errors as cells remain off.

3. Mitigation: Pass-Through Voltage Tuning

Vpass Tuning dynamically learns a safe, low pass-through voltage for each block, using available ECC margin to reduce read-disturb error peaks and extend flash endurance.

  • 3. Mitigation: Pass-Through Voltage Tuning: Vpass Tuning learns the minimum pass-through voltage for each block that still allows all data to be read correctly with ECC.The mechanism adapts its learning process over time as threshold voltages change due to retention loss.
  • 3. Mitigation: Pass-Through Voltage Tuning: The mechanism first estimates each block’s available ECC margin, then calibrates Vpass to introduce no more than that margin’s additional raw errors.It estimates the margin using a predicted worst-case page and calibrates Vpass on a per-block basis.
  • 3. Mitigation: Pass-Through Voltage Tuning: If lowering Vpass introduces an unacceptable number of errors, the mechanism rolls back to a higher value whose errors remain correctable by ECC.The calibration decreases Vpass incrementally, tests the resulting errors, and increases it again when the ECC margin is exceeded.
  • 3. Mitigation: Pass-Through Voltage Tuning: The mechanism checks Vpass daily, increasing it when slowly accumulating retention or read-disturb errors require additional margin.When a block is refreshed, accumulated retention and read-disturb errors are corrected before Vpass is checked again.
  • 3. Mitigation: Pass-Through Voltage Tuning: 21.0% average endurance improvement was achieved across varied real-workload traces with Vpass Tuning.Endurance is measured by the number of program/erase cycles before the flash memory can no longer be used.

4. Read Disturb Oriented Error Recovery

Read Disturb Recovery targets data-loss conditions beyond ECC by identifying disturb-prone cells and probabilistically correcting them so ECC can recover the remaining errors.

  • 4. Read Disturb Oriented Error Recovery: Read Disturb Recovery is designed to recover data after a flash device has exceeded its lifetime and ECC can no longer correct some reads.The paper describes this as recovery beyond the traditional point of data loss.
  • 4. Read Disturb Oriented Error Recovery: RDR identifies cells susceptible to read disturb and probabilistically corrects their data before ECC corrects the remaining errors.The probabilistic step reduces the error count to within ECC’s correction capability.
  • 4. Read Disturb Oriented Error Recovery: Disturb-prone cells undergo larger upward threshold-voltage shifts, causing overlapping data-value distributions and read errors.Disturb-resistant cells shift less, while the overlap between distributions creates ambiguity at read boundaries.
  • 4. Read Disturb Oriented Error Recovery: RDR identifies susceptible cells by inducing additional read disturbs and comparing each cell’s threshold-voltage shift with a boundary threshold.Cells with higher threshold-voltage changes are classified as more susceptible.
  • 4. Read Disturb Oriented Error Recovery: 36% raw bit error-rate reduction was achieved at 1 million read disturb operations in a block with 8,000 P/E cycles of wear.The reduction grew from a few percent at low disturb counts to 36% at the highest reported count.

5. Related Work

Related work spans NAND error characterization and mitigation, DRAM RowHammer, and emerging memories, with NAND and DRAM disturbance mechanisms sharing conceptual similarities but differing in device-level details.

  • 5. Related Work: The related-work review covers six NAND categories, followed by DRAM read disturb errors and emerging memory technologies.The NAND categories include characterization, 3D NAND, mitigation, voltage optimization, and error recovery.
  • NAND Flash Error Characterization: Earlier NAND studies examined read disturb alongside P/E cycling, programming, program interference, and retention errors.These studies also proposed mitigation mechanisms for the different error sources.
  • Read Disturb Error Mitigation: NAND mitigation proposals include caching recently read data, read reclaim, fixed read limits, periodic checks, and mapping read-hot pages to SLC blocks.Prior work also combines read-hot mapping with Vpass Tuning and read reclaim.
  • Voltage Optimization: Voltage-optimization work shares the spirit of Vpass optimization but targets read-reference voltages, including estimates derived from threshold-voltage distribution statistics.The cited approach requires periodically reading and characterizing those distributions.
  • Read Disturb Errors in DRAM: RowHammer is conceptually similar to NAND read disturb, but DRAM disturbance mechanisms and mitigation techniques differ because of device-level differences.Repeated DRAM row activation can flip bits in adjacent rows.
  • Read Disturb Errors in DRAM: In tested DRAM, the number of flipped bits varies substantially within modules, module distributions differ, and more than 80% of tested chips were affected.The review cites experiments across modules from three manufacturers.
  • Read Disturb Errors in DRAM: User-level software has exploited RowHammer to induce DRAM errors and compromise systems, including gaining kernel-level privileges and taking over servers or virtual machines.The paper characterizes RowHammer as a practical system-security vulnerability.
  • Errors in Emerging Memory Technologies: Dependable large-scale reliability studies remain unavailable for real PCM, STT-RAM, RRAM, and memristor chips because these technologies are still nascent.The paper expects conceptually similar error mechanisms may occur, but with different underlying mechanisms and error rates.

6. Significance

The work establishes read disturb as an increasingly important NAND reliability problem and provides characterization data, mitigation, and recovery mechanisms with broader research and storage implications.

  • The DSN 2015 paper was the first openly available work to characterize read disturb in commercial NAND devices and propose solutions.
  • Read disturb adds errors that further reduce NAND flash endurance, especially as technology scaling makes devices more susceptible.
  • RDR may reduce unrecoverable data loss in high-density data-center storage and motivate further recovery mechanisms leveraging intrinsic flash properties.
  • The released characterization examines how pass-through voltage, program/erase cycles, and retention age affect read-disturb-induced errors.

7. Conclusion

The conclusion reports detailed experimental characterization of read disturb in 2Y-nm MLC NAND and uses the findings to guide mitigation and recovery mechanisms. It also argues that continued scaling will increase the need for such mechanisms and for pass-through-voltage controls.

  • The study provides the first detailed experimental characterization of read disturb errors in 2Y-nm MLC NAND flash chips.
  • Read disturb errors are more likely in lower-threshold-voltage and more-worn cells, while reducing pass-through voltage mitigates them.
  • Vpass Tuning dynamically adjusts pass-through voltage online for each block, while Read Disturb Recovery probabilistically corrects susceptible cells.
  • Continued scaling is expected to increase read-disturb susceptibility, motivating pass-through-voltage controls in next-generation chips.
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