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Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation

Yixin Luo, Saugata Ghose, Yu Cai, Erich F. Haratsch, Onur Mutlu

arXiv:1807.05140v2cs.AR

TL;DR

Planar NAND error models and mitigation methods may not capture 3D NAND’s architecture-specific reliability behavior. Through real-chip characterization, the paper identifies new error characteristics, develops analytical models and four mitigation techniques, and reports 1.85× longer lifetime or 78.9% lower correction-storage overhead.

  • Problem

    3D NAND lacks sufficient real-chip error-characterization knowledge, limiting understanding of its reliability relative to planar NAND.

  • Method

    The paper experimentally characterizes real state-of-the-art 3D NAND chips, develops models for process variation and retention loss, and proposes four mitigation techniques.

  • Results

    Compared with a state-of-the-art baseline, the combined techniques improve flash-memory lifetime by 1.85× or reduce error-correction storage overhead by 78.9% at constant lifetime.

  • Takeaways & Limitations

    3D NAND reliability management should account for layer-specific variation, early retention loss, and retention interference rather than relying solely on planar-NAND assumptions.

  • Takeaways & Limitations

    ReNAC shows no meaningful lifetime improvement for the current 3D NAND generation because retention interference shifts threshold voltage by less than two voltage steps.

Abstract

from arXiv · show

Compared to planar (i.e., two-dimensional) NAND flash memory, 3D NAND flash memory uses a new flash cell design, and vertically stacks dozens of silicon layers in a single chip. This allows 3D NAND flash memory to increase storage density using a much less aggressive manufacturing process technology than planar NAND flash memory. The circuit-level and structural changes in 3D NAND flash memory significantly alter how different error sources affect the reliability of the memory. In this paper, through experimental characterization of real, state-of-the-art 3D NAND flash memory chips, we find that 3D NAND flash memory exhibits three new error sources that were not previously observed in planar NAND flash memory: (1) layer-to-layer process variation, where the average error rate of each 3D-stacked layer in a chip is significantly different; (2) early retention loss, a new phenomenon where the number of errors due to charge leakage increases quickly within several hours after programming; and (3) retention interference, a new phenomenon where the rate at which charge leaks from a flash cell is dependent on the data value stored in the neighboring cell. Based on our experimental results, we develop new analytical models of layer-to-layer process variation and retention loss in 3D NAND flash memory. Motivated by our new findings and models, we develop four new techniques to mitigate process variation and early retention loss in 3D NAND flash memory. These four techniques are complementary, and can be combined together to significantly improve flash memory reliability. Compared to a state-of-the-art baseline, our techniques, when combined, improve flash memory lifetime by 1.85x. Alternatively, if a NAND flash vendor wants to keep the lifetime of the 3D NAND flash memory device constant, our techniques reduce the storage overhead required to hold error correction information by 78.9%.

1 INTRODUCTION

3D NAND addresses planar NAND’s scaling and reliability limits through a new architecture, but introduces previously unobserved error characteristics. The paper characterizes real chips, models these effects, and proposes mitigation techniques.

  • 3D NAND was introduced to overcome planar NAND’s density-scaling challenge, but real-chip error characteristics remained insufficiently understood.
  • The middle layer’s raw bit error rate can reach 6× that of the top layer.
  • Early retention loss increases the retention error rate by an order of magnitude within approximately 3 hours after programming.
  • The paper develops analytical models and four techniques—LaVAR, LI-RAID, ReMAR, and ReNAC—to mitigate process variation and retention-related errors.
  • The study identifies layer-to-layer process variation, early retention loss, and retention interference as new 3D NAND error characteristics.
  • Together, the techniques improve flash-memory lifetime by 1.85× or reduce error-correction storage overhead by 78.9% at constant lifetime.

2 BACKGROUND

NAND flash stores data through threshold-voltage states and relies on reference-voltage reads, while fabrication, retention, write, and read processes produce distinct error sources. ECC corrects errors only up to a fixed capability.

  • MLC NAND flash stores two bits per cell by assigning each value to one of four threshold-voltage states.
  • A flash block contains wordlines of cells, with pages forming the unit of data programmed at a time.
  • A controller reads cells by applying reference voltages and detecting whether each cell’s threshold voltage exceeds the applied value.
  • Process variation, retention, write-induced, and read-induced errors arise from fabrication differences, charge leakage, programming or erasing, and read operations.
  • ECC has a fixed correction capability, and a page becomes uncorrectable when its errors exceed that limit.

3 ARCHITECTURAL DIFFERENCES BETWEEN 3D NAND AND PLANAR NAND

3D NAND differs from planar NAND in cell design, chip organization, and manufacturing scale. Its charge-trap cells and vertically stacked layers enable high density with larger cells, while changing physical error behavior.

  • 3D NAND differs from planar NAND in flash-cell design, cell organization, and manufacturing process technology.
  • Flash Cell Design: Most planar NAND uses floating-gate transistors, whereas most 3D NAND uses vertically structured charge-trap transistors.
  • Flash Chip Organization: In 3D NAND, vertically connected bitlines link one charge-trap cell from each stacked layer, while same-layer control gates form wordlines.
  • Manufacturing Process Technology: 3D NAND commonly uses 30–50 nm process technology and 24–96 layers, achieving comparable density with larger cells than 10–15 nm planar NAND.

4 CHARACTERIZATION OF 3D NAND FLASH MEMORY ERRORS

Experiments on real 3D NAND chips identify layer-to-layer process variation, early retention loss, and retention interference as important error characteristics that differ from planar NAND. The measurements motivate models and mitigation mechanisms tailored to these behaviors.

  • 4.2 Layer-to-Layer Process Variation: 3D NAND exhibits significant layer-to-layer variation in RBER and optimal read reference voltage, especially for ER/P1-related states.ER ↔ P1 and P1 ↔ P2 errors vary across layers, while P2 ↔ P3 errors remain similar; optimal Va and Vb vary significantly, whereas Vc changes little.
  • 4.3 Early Retention Loss: 3D NAND retention error rises by an order of magnitude within approximately 3 hours and becomes higher than planar NAND after approximately 2 hours.The error increase is steep at low retention times and flattens at higher retention times, unlike the comparatively slower change observed in planar NAND.
  • 4.3 Early Retention Loss: Optimal read reference voltages Vb and Vc decrease significantly as retention time increases, while Va remains relatively constant.The voltage-retention relationship for Vb and Vc can be modeled logarithmically.
  • 4 CHARACTERIZATION OF 3D NAND FLASH MEMORY ERRORS: The study develops analytical models and four mitigation mechanisms for the newly observed 3D NAND error characteristics.The models estimate RBER, threshold-voltage distributions, and optimal read reference voltages; the mechanisms include LaVAR, LI-RAID, ReMAR, and ReNAC.
  • 4.4 Retention Interference: Retention interference makes a cell’s charge-leakage speed depend on the threshold voltage or state of its vertically adjacent neighbor.Charge leaks more slowly when the neighboring cell is in a higher-voltage state; the study quantifies this effect over 24 days.

5 3D NAND FLASH MEMORY ERROR MODELS

The paper develops analytical models for layer-to-layer RBER variation and retention loss in 3D NAND, using measured data to characterize distributions, voltage optimization, and retention dependence.

  • Layer-to-layer process variation: Layer-to-layer RBER variation is modeled with a gamma distribution rather than a single block-wide RBER value.The model uses shape parameter a to control skew and scale parameter s to control distribution width.
  • Layer-to-layer process variation: Figure 11 compares measured and fitted per-page RBER distributions under variation-agnostic and variation-aware optimal read voltages.The variation-aware voltage is selected per page to minimize its RBER.
  • Layer-to-layer process variation: 0.09 is the KL-divergence error between measured and fitted RBER distributions, while average RBER falls from 1.6 × 10^-4 to 1.4 × 10^-4 with variation-aware Vopt.Some pages still exceed 4 × 10^-4 RBER, well above the average.
  • Retention loss: Retention loss is modeled as a linear function of log retention time for both log(RBER) and threshold voltage, with coefficients dependent on P/E cycle count.The model parameters are fitted using ordinary least squares.
  • Retention loss: The retention model explains more than 89% of characterized variation for most modeled variables, while σER and Va have lower adjusted R^2 because they change little.The authors describe the model as accurate and easy to compute.

6 3D NAND ERROR MITIGATION TECHNIQUES

The paper proposes complementary techniques that adapt reads and redundancy to 3D NAND’s layer variation and retention behavior, reducing error rates and improving system-level reliability.

  • Technique overview: Four techniques target layer variation, retention loss, and retention interference: LaVAR, LI-RAID, ReMAR, and ReNAC.LaVAR and LI-RAID address layer variation; ReMAR addresses retention loss; ReNAC addresses retention interference.
  • LaVAR: LaVAR learns layer-specific voltage offsets and adds them to block-level Vopt during reads, using controller lookup tables without hardware changes.Its lookup table requires 2N bytes for N layers, with negligible read latency overhead.
  • LaVAR: 43.3% is LaVAR’s average RBER reduction across all P/E cycle counts relative to variation-agnostic voltage tuning.The reduction becomes smaller at higher P/E counts because wear-related errors increasingly dominate process-variation errors.
  • System reliability: At 10,000 P/E cycles, worst-case RBER is evaluated because a few least-reliable pages can exceed ECC capability before block-average RBER does.This evaluation motivates techniques that reduce per-page variation, not only average error rates.
  • ReMAR: ReMAR reduces average RBER by 51.9% using retention-aware Vopt based on P/E cycle count and retention time.Its benefit over the retention-agnostic baseline increases as P/E cycle count rises.
  • System reliability: 85.0% is the combined lifetime improvement over Baseline, and the same increase applies to maximum server write frequency under a fixed device lifetime.The lifetime calculation uses an ECC limit of 3 · 10^-3 RBER.
  • ECC overhead: 78.9% is the reduction in ECC redundancy over Baseline when the evaluated SSDs achieve the same lifetime and end-of-life reliability.The paper leaves performance gains from weaker ECC requirements for future work.

7 RELATED WORK

The paper extends NAND error characterization and mitigation research to real 3D NAND devices, focusing on error characteristics that differ from planar NAND. It develops models and mitigation mechanisms tailored to these new characteristics.

  • 3D NAND Flash Memory Error Characterization: The paper reports the first extensive characterization of layer-to-layer process variation, early retention loss, and retention interference in 3D NAND flash memory.These three error characteristics are presented as new in 3D NAND flash memory.
  • Planar NAND Flash Memory Error Characterization: Prior planar NAND studies characterized cycling, programming, interference, retention, and read-disturb errors using raw bit error rates and threshold-voltage changes.
  • Planar NAND Error Modeling and Mitigation: The paper develops a unified 3D NAND model for retention loss and wearout affecting RBER, threshold-voltage distributions, and Vopt.The model is simpler than some planar-NAND models because the tested 3D NAND chips do not exhibit programming errors.
  • Planar NAND Error Modeling and Mitigation: Prior planar-NAND mitigation techniques are less effective in 3D NAND than the paper’s techniques because 3D NAND has new error characteristics.
  • 3D NAND Flash Memory Error Mitigation: Prior 3D NAND work used different read reference voltages across layers, whereas this paper’s LaVAR mechanism learns and uses layer-specific Vopt values in a lookup table.

8 CONCLUSION

The paper characterizes three new 3D NAND error characteristics, models process variation and early retention loss, and proposes four mitigation techniques. The models predict read-reference voltage and raw bit error rate from retention time and layer number, while the techniques improve reliability.

  • The paper identifies layer-to-layer process variation, early retention loss, and retention interference through experiments on real state-of-the-art 3D NAND chips.
  • The paper attributes these error characteristics to architectural changes from planar to 3D NAND flash memory.
  • The analytical models predict optimal read reference voltage and raw bit error rate using retention time and flash-memory-page layer number.
  • Four new error-mitigation techniques use the models and successfully mitigate the new error patterns observed in 3D NAND flash memory.

A.1 Write-Induced Errors

This section examines write-induced errors through their effects on raw bit error rate and threshold-voltage distributions, including program errors caused by multi-step programming.

  • The analysis evaluates how each write-induced error affects RBER and the threshold-voltage distribution of 3D NAND flash memory.
  • Program errors occur when data is written incorrectly, particularly when multiple programming operations are required for one cell.
  • In MLC NAND, two-step programming writes the LSB and MSB through separate partial-programming steps.

A.1.1 Program Errors.

Current 3D NAND devices use one-shot programming and therefore do not exhibit program errors in the tested generation, although future devices may introduce them during continued scaling.

  • Current 3D NAND devices use one-shot programming, writing the LSB and MSB simultaneously, and do not experience program errors.Measurements confirm the lack of program errors in the tested 3D NAND devices.
  • The tested 3D NAND devices lack the secondary threshold-voltage peaks associated with program errors in MLC NAND.
  • Program errors may appear in future 3D NAND generations if continued density scaling leads vendors to adopt two-step programming.The paper connects this possibility to increasing difficulty in adding more layers.

A.1.2 Program/Erase Cycling Errors.

Program/erase cycling progressively shifts and broadens threshold-voltage distributions, increasing RBER and changing which read references are optimal. ER↔P1 errors become especially prominent as cycling accumulates.

  • Threshold-voltage means and standard deviations for all states increase linearly with P/E cycle count.The model fits measured distributions using linear regression.
  • ER↔P1 errors increase faster than other state-transition errors as P/E cycling increases.Wearout prevents cells from reaching very low threshold voltages, shifting and widening the ER distribution.
  • Both LSB and MSB RBER increase exponentially with P/E cycle count, while MSB errors average 2.1× higher than LSB errors.ER↔P1 errors become the dominant MSB error type at 8K P/E cycles.
  • After 16K P/E cycles, the optimal Va read voltage rises by more than 20 voltage steps, while Vb and Vc remain almost constant.The three reference voltages correspond to Va, Vb, and Vc.
  • 3D NAND differs from planar NAND because P2 and P3 threshold-voltage distributions shift lower as cycling increases.The comparison is based on prior planar-NAND observations and the paper’s 3D-NAND measurements.

A.1.3 Program Interference.

Program interference changes a victim cell’s threshold voltage according to the aggressor cell’s programming and physical relationship. In 3D NAND, adjacent-cell interference is weaker than in comparable planar NAND.

  • Victim-cell threshold-voltage shift correlates with the threshold-voltage change of the programmed aggressor cell.The analysis measures this relationship for wordline-to-wordline and bitline-to-bitline interference.
  • A directly adjacent next-wordline aggressor produces a 2.7% interference correlation in the illustrated victim cell.A victim-cell shift of 0.027∆V follows an aggressor-cell shift of ∆V.
  • Next-wordline interference decreases when the victim cell occupies a higher-voltage state.The smaller voltage difference between aggressor and victim likely reduces the induced threshold-voltage shift.
  • Previous-wordline interference substantially affects only ER-state victims and has little effect on P1, P2, or P3 distributions.Programming can only increase a cell’s voltage, so later programming can absorb earlier interference for higher target states.
  • Maximum adjacent-cell interference correlation is 40% lower in 3D NAND than in planar NAND: 2.7% versus 4.5%.The interference effect also decreases as P/E cycle count increases because wearout reduces the aggressor’s voltage change.

A.2 Early Retention Loss

Early retention loss causes threshold-voltage distributions to shift rapidly soon after programming, producing substantial retention-error and read-reference changes. Retention errors are especially associated with P2↔P3 transitions.

  • At low retention times, threshold-voltage distributions shift more because charge trapped near the charge-trap surface detrapps soon after programming.As retention time increases, P1, P2, and P3 voltages decrease while ER voltage increases.
  • Retention errors are dominated by P2↔P3 transitions in a block subjected to 10K P/E cycles.The P3 distribution shifts substantially during retention.
  • 3D NAND retention loss shifts P1, P2, and P3 distributions lower while having little effect on each distribution’s width.This differs from the retention-loss behavior reported for planar NAND.
  • Early retention loss changes flash-cell threshold voltage quickly within several hours after programming, significantly changing RBER and optimal read-reference voltages.The phenomenon is attributed to rapid early charge detrapping.

A.3 Read-Induced Errors

Read errors occur when repeated reads use a reference voltage close to a cell’s threshold voltage, allowing the same cell to return different data values. These errors add uncertainty to every SSD-controller read operation and remain understudied.

  • A read error occurs when two reads return different data values because the reference voltage is close to the cell’s threshold voltage.The error adds uncertainty to the outcome of each read operation performed by the SSD controller.
  • Read errors can affect every SSD-controller read operation, yet prior work has not studied them extensively.

A.3.1 Read Errors.

The paper characterizes read, read-disturb, and process-variation effects in 3D NAND flash, showing how these effects alter error rates and read-reference voltages. Read errors correlate with read offset and RBER, while layer-to-layer variation is more consequential than bitline-to-bitline variation.

  • Read errors: Read error rate decreases exponentially as the absolute read offset (Vref −Vth) increases.When Vref is closer to Vth, increased sense-amplifier noise raises the likelihood of a read error.
  • Read errors: Read error rate is linearly correlated with the overall RBER of a flash page.Higher RBER increases overlap between neighboring threshold-voltage distributions, placing more cells near the read reference voltage.
  • Read disturb: At 10K P/E cycles, the RBER sensitivity to read disturb is 96.7% lower in 3D NAND than in comparable planar NAND.RBER still increases linearly with read disturb count in both technologies.
  • Layer-to-layer process variation: Layer-to-layer process variation changes threshold-voltage distributions and produces large variations in RBER and optimal read-reference voltages.The ER-state mean threshold voltage varies by as much as 25 voltage steps across layers, while other state means vary little.
  • Bitline-to-bitline process variation: Bitline-to-bitline process variation is much smaller than layer-to-layer process variation because RBER and optimal read-reference voltages change little across bitlines.The bitline analysis examines RBER by state transition and by MSB or LSB page.
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