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Direct randomized benchmarking for multi-qubit devices

Timothy J. Proctor, Arnaud Carignan-Dugas, Kenneth Rudinger, Erik Nielsen, Robin Blume-Kohout, Kevin Young

arXiv:1807.07975v3quant-ph

TL;DR

Clifford randomized benchmarking becomes difficult to scale because its multi-qubit Clifford gates must be compiled into native gates. This paper introduces direct randomized benchmarking using random circuits over native gates, and demonstrates it experimentally on 2–5 qubits. The protocol also supports configurable estimates of error rates for distinct gate sets.

  • Problem

    Clifford randomized benchmarking requires compiled multi-qubit Clifford gates whose depth and infidelity grow with qubit count, limiting practical holistic benchmarking.

    Source: p. 1

  • Method

    Direct randomized benchmarking samples variable-length circuits from a device’s native gates and estimates an error rate from exponential decay.

    Source: p. 2

  • Results

    DRB produced an exponential decay and a reasonably precise error-rate estimate in experiments on 2–5 qubits.

    Source: p. 3

  • Takeaways & Limitations

    DRB’s configurable sampling supports estimating error rates for distinct gate sets, including an average CNOT error rate.

    Source: pp. 3, 5

    With coherent errors, connecting the measured decay rate to a formal gate-error rate remains subtler and is deferred to future work.

    Source: p. 5

Abstract

from arXiv · show

Benchmarking methods that can be adapted to multi-qubit systems are essential for assessing the overall or "holistic" performance of nascent quantum processors. The current industry standard is Clifford randomized benchmarking (RB), which measures a single error rate that quantifies overall performance. But scaling Clifford RB to many qubits is surprisingly hard. It has only been performed on 1, 2, and 3 qubits as of this writing. This reflects a fundamental inefficiency in Clifford RB: the $n$-qubit Clifford gates at its core have to be compiled into large circuits over the 1- and 2-qubit gates native to a device. As $n$ grows, the quality of these Clifford gates quickly degrades, making Clifford RB impractical at relatively low $n$. In this Letter, we propose a direct RB protocol that mostly avoids compiling. Instead, it uses random circuits over the native gates in a device, seeded by an initial layer of Clifford-like randomization. We demonstrate this protocol experimentally on 2 -- 5 qubits, using the publicly available IBMQX5. We believe this to be the greatest number of qubits holistically benchmarked, and this was achieved on a freely available device without any special tuning up. Our protocol retains the simplicity and convenient properties of Clifford RB: it estimates an error rate from an exponential decay. But it can be extended to processors with more qubits -- we present simulations on 10+ qubits -- and it reports a more directly informative and flexible error rate than the one reported by Clifford RB. We show how to use this flexibility to measure separate error rates for distinct sets of gates, which includes tasks such as measuring an average CNOT error rate.

SUPPLEMENTAL MATERIAL

The supplemental material provides implementation and analysis details for the main experiments and simulations. It also adds a simulation illustrating estimation of error rates for different gate sets.

SUPPLEMENTAL MATERIAL

  • The supplement details the DRB sampling, experiments, and analyses, with accompanying data and Python code.It includes decay curves for the second sampling distribution used in the main text.Source: SUPPLEMENTAL MATERIAL · p. 8
  • A five-qubit simulation with realistic connectivity, gate-dependent high error rates, and realistic state-preparation and measurement errors illustrates estimating error rates for different gate sets.The example validates the estimation method used to analyze the main-text experimental data.Source: SUPPLEMENTAL MATERIAL · p. 8
  • The supplement describes the random-circuit sampling implementations used for the experimental demonstration and DRB and CRB simulations.Source: SUPPLEMENTAL MATERIAL · p. 8

Circuit sampling methods

The section describes how DRB and CRB circuits are sampled and implemented, including stabilizer-state preparation, Clifford representations, and compilation. The sampling code is integrated into pyGSTi and publicly available.

Circuit sampling methods

  • The circuit-sampling code is integrated into the publicly available pyGSTi package.Efficient sampling and compilation are required to implement DRB and CRB.Source: Circuit sampling methods · p. 8
  • A DRB circuit samples a stabilizer state, prepares it with native gates, applies m layers drawn from Ω, and computes the final stabilizer state.Source: Circuit sampling methods · p. 8
  • A CRB circuit uniformly samples m Clifford gates, computes an inverting Clifford, and compiles all m + 1 Cliffords into native-gate circuits.Source: Circuit sampling methods · p. 8
  • Cliffords are represented by a symplectic matrix and a vector, enabling sequence composition and inversion through matrix operations and explicit formulas.Source: Circuit sampling methods · p. 8
  • Uniform stabilizer-state sampling is implemented by uniformly sampling a Clifford and applying it to |0⟩^n.The text notes that more computationally efficient stabilizer-state sampling methods exist.Source: Circuit sampling methods · p. 8
  • The Clifford compiler uses randomized Gaussian elimination and O(n^2) one- and two-qubit gates, rather than the asymptotically optimal O(n^2/log n) scaling.Randomized qubit labeling is used to seek lower-CNOT compilations.Source: Circuit sampling methods · pp. 8–9
  • The stabilizer-state compiler also uses Gaussian elimination and O(n^2) CNOT gates, supporting a reasonably fair DRB–CRB comparison.The authors say complete fairness is unclear without optimal stabilizer-state and Clifford compilers; the method also heuristically reduces connectivity-related swap overhead.Source: Circuit sampling methods · p. 9

Simulations

The supplemental simulations include a five-qubit example with realistic connectivity and gate-dependent errors.

Simulations

  • The additional simulation uses five qubits, realistic connectivity, gate-dependent high error rates, and realistic state-preparation and measurement errors.Source: Simulations · p. 9

Methods

The simulations use an efficient-in-n simulator for Pauli-stochastic gate errors, and the authors note that broader error models can also be simulated for moderate qubit counts. They report that DRB has behaved broadly reliably across a range of simulated error models, including coherent errors.

Methods

  • The simulations model Pauli-stochastic gate and, in one case, measurement errors by sampling errors and propagating them through Clifford circuits.The simulator’s error probabilities can depend on the applied gate.Source: Methods · p. 9
  • Although the reported simulations use Pauli-stochastic errors, pyGSTi also supports pure-state and density-matrix simulations for more general error models at moderate qubit counts.Source: Methods · p. 9
  • The authors report that DRB has been broadly reliable in simulations across varied error models, including purely coherent errors; further simulations are deferred to future papers.Source: Methods · p. 9

An additional simulated example of DRB and CRB

A five-qubit simulation with strong, gate-dependent stochastic errors shows DRB retaining usable exponential-decay estimates where CRB does not. Changing DRB’s sampling distribution also allows estimation of distinct gate-class and average CNOT error rates.

Experiments

On IBMQX5, 2–5-qubit DRB experiments compared two CNOT sampling probabilities; lower CNOT sampling yielded substantially lower error rates, and the datasets were used to estimate average CNOT error rates.

Experiments

  • Each IBMQX5 experiment used 28 circuits per length, lengths from m=0 to 30 in steps of 5, and 1024 counts per circuit.The circuits were sampled using code integrated into pyGSTi; data and analysis notebooks were available in the paper’s ancillary files.Source: Experiments · p. 11
  • Each layer used a p_CNOT-biased coin to decide whether to add one uniformly chosen CNOT, with random one-qubit Cliffords on the other qubits or on every qubit otherwise.The benchmarked subset contained between one and five possible CNOT gates, depending on the number of qubits.Source: Experiments · p. 12
  • The DRB error rates with p_CNOT=0.25 were 1/2–1/3 those with p_CNOT=0.75, alongside an expected one-third as many CNOTs in the central circuit.The paired datasets were also used to estimate average CNOT error rates in n-qubit circuits.Source: Experiments · p. 12, Figure 5 · p. 12
  • Recalibration between the two datasets changed average CNOT error rates by no more than approximately 0.2%, a qualification the authors considered acceptable for a demonstration rather than a comprehensive IBMQX5 benchmark.The reported average CNOT error rate across the benchmarked qubits ranged from approximately 3.6% to 4.5% as n increased from 2 to 5.Source: Experiments · p. 12
  • Calibration-based DRB predictions assume isolated one- and two-qubit error rates predict n-qubit gates formed by parallel applications of those gates.The calibration data supplied readout and one-qubit error rates per qubit and CNOT error rates; the predicted DRB rate was r≈ε_Ω.Source: Experiments · pp. 12–13
  • Crosstalk-free simulations using calibration-consistent errors on both experimental and independently sampled circuits produced DRB rates consistent with the calibration-based predictions.The simulations were used to assess whether the observed discrepancy could reflect a failure of DRB.Source: Experiments · p. 13
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