Source-linked AI summary
p-Bits for Probabilistic Spin Logic
Kerem Y. Camsari, Brian M. Sutton, Supriyo Datta
TL;DR
The paper introduces p-bits as fluctuating units between conventional bits and q-bits, addressing the need for stochastic devices with input-controlled outputs. It proposes low-barrier-magnet and transistor implementations, with simulations indicating p-circuits can support machine-learning and optimization applications at room temperature.
Problem
Probabilistic circuits need three-terminal devices whose inputs bias stochastic outputs, connecting stochastic machine learning and quantum-computing applications.
Method
The paper uses low-barrier magnets and fluctuating resistive elements with transistors to construct p-bits and p-circuits, using weighted networks to realize Boolean and inverse operations.
Results
Initial full-SPICE demonstrations indicate that optimization problems, including quantum annealing, are amenable to p-bit implementations scalable at room temperature; inverse gates can enumerate inputs consistent with an output.
Takeaways & Limitations
P-bits bridge stochastic machine learning and quantum computing, while supporting applications such as BSN acceleration, subset-sum solving, and factorization.
Abstract
from arXiv · showhide
We introduce the concept of a probabilistic or p-bit, intermediate between the standard bits of digital electronics and the emerging q-bits of quantum computing. We show that low barrier magnets or LBM's provide a natural physical representation for p-bits and can be built either from perpendicular magnets (PMA) designed to be close to the in-plane transition or from circular in-plane magnets (IMA). Magnetic tunnel junctions (MTJ) built using LBM's as free layers can be combined with standard NMOS transistors to provide three-terminal building blocks for large scale probabilistic circuits that can be designed to perform useful functions. Interestingly, this three-terminal unit looks just like the 1T/MTJ device used in embedded MRAM technology, with only one difference: the use of an LBM for the MTJ free layer. We hope that the concept of p-bits and p-circuits will help open up new application spaces for this emerging technology. However, a p-bit need not involve an MTJ, any fluctuating resistor could be combined with a transistor to implement it, while completely digital implementations using conventional CMOS technology are also possible. The p-bit also provides a conceptual bridge between two active but disjoint fields of research, namely stochastic machine learning and quantum computing. First, there are the applications that are based on the similarity of a p-bit to the binary stochastic neuron (BSN), a well-known concept in machine learning. Three-terminal p-bits could provide an efficient hardware accelerator for the BSN. Second, there are the applications that are based on the p-bit being like a poor man's q-bit. Initial demonstrations based on full SPICE simulations show that several optimization problems including quantum annealing are amenable to p-bit implementations which can be scaled up at room temperature using existing technology.
A. Between a bit and a q-bit
The paper positions classical, rapidly fluctuating p-bits between deterministic bits and cryogenic q-bits, proposing room-temperature probabilistic computing with existing technology. Low-barrier magnets can implement p-bits whose transistor-integrated forms support interconnected p-circuits.
- Conceptual position: P-bits are classical entities that fluctuate rapidly between 0 and 1, occupying a conceptual position between digital bits and q-bits.Unlike q-bits, p-bits are envisioned to operate robustly at room temperature using existing technology.
- Physical basis: A nanomagnet’s switching rate depends exponentially on its energy barrier, so barrier engineering determines whether it behaves as long-term or short-term memory.With τ0 of one nanosecond, barriers near 40 kBT correspond to roughly 10 years, whereas 14 kBT corresponds to roughly 1 ms.
- Physical basis: Low-barrier magnets reduce magnetic stability by shrinking volume or anisotropy and can use near-transition perpendicular magnets or circular in-plane magnets.The paper collectively calls these implementations LBM’s rather than superparamagnets.
- Circuit architecture: LBM-based p-bits can be incorporated into transistor-like three-terminal structures and interconnected into p-circuits that perform useful functions.The paper notes that the physical implementation need not use spins or spintronics; fluctuating non-spintronic devices are also feasible.
- Motivation: The proposed p-computer addresses networks of probabilistic quantities that require efficient simulation and is motivated by Feynman’s description of probabilistic computers.The p-bit framework is presented as a bridge between classical probabilistic computing and quantum computing.
B. Binary stochastic neuron (BSN)
The paper connects p-bits to binary stochastic neurons and focuses on unclocked, asynchronous hardware accelerators for their stochastic updates. It also identifies clocked sequencing as a practical alternative when synaptic delays disrupt natural asynchronous operation.
- BSN model: A binary stochastic neuron produces a bipolar stochastic response from a weighted input and a uniformly distributed random number.The paper uses mi = ±1 for the two states; a 0,1 representation would use a different equation.
- Hardware acceleration: Three-terminal p-bits could accelerate the stochastic response equation, while synaptic hardware supplies the weighted-input function, together forming a probabilistic computer.The accelerator requires a tunable random source whose output is biased by the input Ii, not merely an independent RNG.
- Operation: The paper focuses on unclocked asynchronous LBM-based hardware accelerators for BSNs and reports sequential updating in SPICE simulations and Arduino-based emulations when synaptic delay is sufficiently short.This asynchronous operation is used to highlight p-bits as a bridge between stochastic machine learning and quantum computing.
- Practical boundary: Most practical applications will probably use clocked sequential updates because unclocked operation is rare in digital systems.Synchronous operation is particularly useful when synaptic delays interfere with natural asynchronous behavior.
A. Three-terminal p-Bit
A three-terminal p-bit combines a fluctuating low-barrier element with input biasing and output readout, using an MTJ-transistor structure that resembles embedded MRAM. The transistor tunes stochastic output statistics, while device design must address magnet pinning and response dynamics.
- A three-terminal p-bit requires a stochastic element with separate input and output terminals for biasing and reading its state.
- A tunable RNG can be built by placing a fluctuating resistance in series with a transistor, closely resembling the 1T/MTJ structure used in MRAM.The MTJ free layer is replaced with a low-barrier magnet, and an inverter can amplify drain fluctuations.
- The transistor resistance tunes the stochastic output: fluctuations are largest when RT ∼ RP or RAP and suppressed when RT ≪ RP or RT ≫ RAP.An added inverter produces an output approximately described by the BSN relation using scaled circuit voltages.
- The fluctuating MTJ resistance is governed by instantaneous magnetization calculated from the spin-current-driven sLLG equation.
- Low-barrier magnets require careful design to minimize pinning near zero input voltage, particularly for low-barrier perpendicular magnets.Circular in-plane magnets generally avoid this issue because of their strong demagnetizing field.
- Changing Vin,i changes output-voltage statistics within tens of picoseconds, while magnet fluctuations determine the random-number correlation time.The fast response is set by typical transistor switching speeds and does not depend on magnet fluctuation rates.
- P-bits can also use non-spintronic fluctuating resistors, including CMOS-based units, rather than MTJs.
B. Weighted p-bit
Weighted p-bits integrate synaptic weighting with neuron operation by summing multiple inputs into a bias voltage. Floating-gate capacitances or resistor networks set the weights, subject to device and routing constraints.
- A weighted p-bit integrates the neuron and relevant synapse components by summing inputs into the bias voltage VIN,i.Floating-gate devices can implement this integration for inputs indexed from 1 to n.
- Scaling Vin and Vout lets circuit voltages play the roles of the BSN input Ii and output mi, recasting the hardware relation in the form of the weighted-neuron equation.
- The weights Wij are adjusted through connected capacitors Cij, while routing topology and neuMOS device size limit the available weights and connections.
- When C0 ≫ ΣCij, the capacitive weights approximately satisfy Wi,j ≈ Ci,j/C0; weighted designs can also operate without this assumption.
- Resistor networks provide analogous weight control by replacing capacitances Cij with conductances Gij.
- FET input conductance is typically too low for the required G0 ≫ ΣGij condition, so an external conductance must be added.
III. APPLICATIONS OF P-CIRCUITS
P-circuit applications can use compact p-bit hardware with local synapses to avoid repeated data transfers between neuron and synapse computations. Demonstrations use full SPICE simulations of embedded MTJ-based p-bits and asynchronous circuits.
- A compact p-bit with a local synapse can serve as a hardware accelerator by reducing data transfers between neuron and synapse computations.Synapses may otherwise be implemented off-chip in software or with a hardware matrix multiplier.
- Illustrative results are obtained from full SPICE simulations coupling the stochastic Landau-Lifshitz-Gilbert equation with PTM-based transistor models.
A. Applications: Machine learning inspired
The paper presents p-circuits as hardware networks for Bayesian inference and neural-network learning, using correlations among stochastic nodes and repeated inference operations. Genetic relatedness provides an illustrative Bayesian circuit, while restricted Boltzmann-machine training motivates hardware acceleration.
- Bayesian inference: Siblings have 50% relatedness, while an aunt and nephew have 25% relatedness when the relevant parents are uncorrelated.The sibling result follows from averaging independent parental contributions.
- Bayesian inference: A p-circuit can represent each stochastic node with a hardware p-bit interconnected according to genetic influences.The paper frames the genetic circuit as an illustration of nodal correlations in stochastic networks.
- Bayesian inference: XNOR or AND gates multiply bipolar or binary node values, and a long-time-constant RC circuit computes their time average.The gate choice depends on whether variables use −1/+1 or 0/1 representations.
- Bayesian inference: SPICE simulations agree well with Bayes theorem even though the p-circuit operates asynchronously without sequencers.The cited circuit results use hardware multiplication and time averaging to estimate correlations.
- Accelerating learning algorithms: Networks of p-bits could accelerate inference tasks after their weights are trained offline in software.The proposed use separates offline learning from repeated hardware inference.
- Accelerating learning algorithms: Restricted Boltzmann-machine learning repeatedly evaluates correlations, whose exponential complexity motivates efficient physical representations of neurons and synapses.Contrastive divergence limits repeated evaluations with a fixed number of steps, denoted CDn.
B. Applications: Quantum inspired
The paper presents p-bit networks for invertible Boolean logic and classical or quantum-inspired optimization, using weighted interactions to favor desired low-energy states. Simulations demonstrate inverse computation, a 5-city TSP solution, and p-circuit behavior comparable to quantum annealers for stoquastic problems.
- Statistical-physics basis: Symmetric weight matrices connect p-bit networks to statistical-physics models whose equilibrium probabilities follow the Boltzmann law.Reciprocal connections permit an energy-based description of network configurations.
- Invertible Boolean logic: A six-p-bit gate implements XNOR, AND, and OR functions, with a handle bit removing complementary low-energy states outside the truth table.The inputs and outputs can be clamped or allowed to fluctuate according to the desired operating mode.
- Invertible Boolean logic: In inverse mode, clamping an output makes the corresponding input combinations fluctuate, enabling inverse operations unavailable with standard Boolean gates.The same framework is discussed for subset-sum and factorization problems, though scaling factorization remains unexplored.
- Combinatorial optimization: A 5-city TSP is mapped to 16 p-bits and annealed by gradually increasing the interaction parameter I0 to guide the network toward its lowest-energy state.Each p-bit uses indices for visit order and city, and city 0 is fixed.
- Combinatorial optimization: Larger p-bit optimization networks can become trapped in metastable states instead of reaching the lowest-energy configuration.The paper identifies this as a scaling concern for classical annealing.
- Quantum annealing: For stoquastic Hamiltonians, p-circuit SPICE simulations produce correlations and averages comparable to those obtained with quantum annealers.The mapping uses a larger classical p-bit network to approximate the quantum system.
IV. CONCLUSIONS
The paper introduces p-bits as room-temperature probabilistic devices built from low-barrier magnets and transistor-connected fluctuating elements. It positions p-circuits as a bridge between stochastic machine learning and quantum computing, with simulations indicating several optimization applications are feasible.
- Hardware platform: Low-barrier magnets provide a physical representation for p-bits, including perpendicular magnets near the in-plane transition and circular in-plane magnets.MTJs using low-barrier free layers can combine with NMOS transistors into three-terminal building blocks.
- Hardware platform: A p-bit can also use any fluctuating resistor combined with a transistor, while fully digital CMOS implementations are possible.The paper therefore does not restrict p-bit implementations to MTJs or spintronic devices.
- Applications: P-bits bridge stochastic machine learning and quantum computing through their similarity to binary stochastic neurons and their analogy to q-bits.Three-terminal p-bits could provide hardware acceleration for binary stochastic neurons.
- Applications: Full SPICE simulations indicate that several optimization problems, including quantum annealing, are amenable to p-bit implementations scalable at room temperature with existing technology.This is presented as an initial demonstration rather than a completed large-scale hardware result.