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FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks
Michaela Blott, Thomas Preusser, Nicholas Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu
TL;DR
Deploying DNNs is constrained by compute, storage, power, throughput, and latency, motivating reduced-precision neural networks and customized FPGA inference. FINN-R provides an end-to-end framework for exploring and automatically generating such accelerators across precisions, architectures, and platforms. Its evaluated designs reach 50 TOp/s on AWS F1 and 5 TOp/s on embedded platforms, while the explored design space remains incomplete.
Problem
DNN deployment must balance compute, storage, cost, power, throughput, and latency, while identifying the best neural-network and hardware trade-off under task-specific constraints remains difficult.
Method
FINN-R uses a quantization-aware intermediate representation with modular frontends, transformations, backends, cost models, and automated accelerator generation for varied precisions and platforms.
Results
50 TOp/s on datacenter platforms and 5 TOp/s on embedded platforms were measured across four reduced-precision neural networks and multiple platforms.
Takeaways & Limitations
Reduced-precision FPGA accelerators provide substantial performance, power, storage, and hardware-cost trade-offs for customized inference designs.
Takeaways & Limitations
The design-space spectrum remains vast, with many variants unexplored, while tighter performance and resource predictions and improved quantization methods remain future work.
Abstract
from arXiv · showhide
Convolutional Neural Networks have rapidly become the most successful machine learning algorithm, enabling ubiquitous machine vision and intelligent decisions on even embedded computing-systems. While the underlying arithmetic is structurally simple, compute and memory requirements are challenging. One of the promising opportunities is leveraging reduced-precision representations for inputs, activations and model parameters. The resulting scalability in performance, power efficiency and storage footprint provides interesting design compromises in exchange for a small reduction in accuracy. FPGAs are ideal for exploiting low-precision inference engines leveraging custom precisions to achieve the required numerical accuracy for a given application. In this article, we describe the second generation of the FINN framework, an end-to-end tool which enables design space exploration and automates the creation of fully customized inference engines on FPGAs. Given a neural network description, the tool optimizes for given platforms, design targets and a specific precision. We introduce formalizations of resource cost functions and performance predictions, and elaborate on the optimization algorithms. Finally, we evaluate a selection of reduced precision neural networks ranging from CIFAR-10 classifiers to YOLO-based object detection on a range of platforms including PYNQ and AWS\,F1, demonstrating new unprecedented measured throughput at 50TOp/s on AWS-F1 and 5TOp/s on embedded devices.
1 INTRODUCTION
FINN-R addresses the challenge of identifying neural-network and hardware implementations that balance accuracy, performance, cost, power, and latency under application-specific constraints. It combines reduced-precision arithmetic with automated exploration and customized FPGA accelerator generation.
- Motivation: DNN deployment faces compute, storage, cost, power, throughput, and latency constraints across embedded and cloud applications.Offloading to the cloud can also introduce energy and data-transmission overheads that are unsuitable for low-latency or safety-critical use.
- Motivation: Quantized arithmetic reduces memory footprint and can increase performance and energy efficiency by keeping models on-chip and reducing off-chip accesses.Quantized models can exploit higher on-chip bandwidth and improve compute-resource utilization.
- Quantized performance: 87× peak compute performance is achieved on AWS F1 when moving from half-precision floating point to reduced-precision fixed point.For 1-bit variants of ResNet-50, ResNet-152, and Tiny YOLO, increased arithmetic intensity makes implementations no longer memory bound.
- Accuracy trade-offs: Reduced precision causes a slight accuracy impact, addressed through quantization-aware training, numerical representations, and quantization schemes.The cited comparison concerns published ImageNet top-5 error rates for 32-bit and reduced-precision networks.
- Accuracy trade-offs: For a maximum ImageNet error of 10%, the most cost-efficient implementation uses a 2b/8b representation.The design space contains Pareto-optimal reduced-precision trade-offs under hardware-cost or energy-budget constraints.
- FINN-R approach: FINN-R uses a quantization-aware intermediate representation and modular frontend, transformation, and backend structure to explore and generate customized QNN accelerators.The framework supports mixed and variable precisions beyond binary and targets different platforms and design objectives.
2 BACKGROUND
This background reviews quantized neural-network accuracy, FPGA accelerator architectures, and frameworks that transform network descriptions into hardware. It positions FINN-R around flexible precision and customizable accelerator generation across platforms and design goals.
- Quantized Neural Networks: QNNs achieve nearly state-of-the-art accuracy on MNIST, SVHN, and CIFAR-10, while newer quantization schemes also show promising ImageNet results.HWGQ networks with binary weights and 2-bit activations reported less than a 5% top-5 accuracy drop versus floating-point networks on ImageNet.
- Quantized Neural Networks: FINN-R focuses on quantized values using fixed integer representations below 8 bits, while allowing some layers to retain higher or floating-point precision.The notation W x A y denotes layers with x-bit weights and y-bit activations; fixed-point scaling factors can be absorbed into thresholds.
- Accelerator Architectures: FPGA CNN accelerators comprise single processing engines, streaming architectures, or vector processors, representing distinct approaches to organizing computation.Streaming designs use one processing engine per layer with data streamed through the architecture, whereas single engines process layers sequentially.
- Accelerator Architectures: Prior FPGA work demonstrates strong results across these architectures, including up to 1.62× performance density for SDF designs and 255K frames per second for streaming MNIST inference.Other examples include a reported 3× speedup for a systolic-array design and 2.5× better energy efficiency for a 16-bit fixed-point accelerator.
- Accelerator Frameworks: Accelerator frameworks convert graph-based neural-network descriptions into hardware implementations, with FINN-R supporting arbitrary precision, two backend architectures, and multiple target platforms.These frameworks may use fixed architectures or customize hardware for throughput, latency, or power reduction; related tools include DNNWeaver and fpgaConvNet.
3 INFERENCE ACCELERATOR ARCHITECTURE
The architecture maps quantized neural-network layers onto configurable FPGA components and uses microbenchmarks to model their resource costs. Dataflow and multilayer-offload designs provide different resource-scaling behaviors, while FINN-R targets low-precision implementations whose costs depend on precision, parallelism, and buffering.
- 3.1 Microbenchmarks and Operation Cost Function: Microbenchmarks model dot-product complexity as C = N · W · A, with LUT costs roughly proportional to the number of bit-matrix elements.Measurements cover dot-product sizes N and operand widths W × A across multiple precisions.
- 3.1 Microbenchmarks and Operation Cost Function: 45% resource overhead is measured for the HLS implementation compared with the VHDL implementation.The overhead is attributed to HLS reducing partial products to conventional binary numbers before adder-tree accumulation.
- 3.1 Microbenchmarks and Operation Cost Function: 35% higher LUT cost occurs when moving from conventional 1-bit weights to binary weights, followed by 20% increases for ternary and 2-bit precisions.The binary-weight increase is linked to the extra sign bit required for negative multiples, except in the trivial 1-bit-activation case.
- 3.2 Layers: A processing element performs Q parallel multiplications, reduces them through an adder tree, and applies thresholds; P processing elements form an MVU.Additional concurrency supports computing multiple output pixels that share input data.
- 3.2 Layers: The SWU generates interleaved-channel sliding-window vectors, reducing buffer requirements and latency relative to full image buffers.It retains only as many consecutive rows as the convolutional kernel height, plus an extra row for incoming data.
- 3.2 Layers: Convolutional layers combine SWU, MVU, and weight and threshold memories, while maxpool and fully connected layers use smaller component sets.Layer cost is modeled as the sum of basic component costs; MVU BRAM and weight-memory logic costs are negligible.
- 3.2 Layers: Thresholding becomes expensive as output precision rises because the number of stored and compared thresholds grows exponentially.For the targeted small precisions, threshold costs are usually minor, but precisions significantly above 4 bits can make thresholding expensive or infeasible.
- 3.3 Full Inference Accelerator Architecture: Dataflow resource cost sums across layers, whereas multilayer offload cost is determined by the maximum scheduled-layer cost, improving scalability for deep CNNs.The two architectures are endpoints in a broader design space; dataflow is expected to reduce interlayer buffering and latency, though the latency benefit remains unconfirmed experimentally.
4 FINN-R
FINN-R is an end-to-end framework for exploring and generating customized FPGA implementations of quantized neural networks. Its quantization-aware intermediate representation, modular passes, cost analysis, and backend generation support hardware customization across design targets and architectures.
- 4 FINN-R: FINN-R answers which hardware implementation best satisfies specified design constraints for a given neural network.It provides estimates, automates hardware customization, and supports interactive exploration of platforms, architectures, and precisions.
- 4 FINN-R: FINN-R uses modular frontends, transformation and analysis passes, and backends inspired by LLVM compiler infrastructure.Passes can transform the QNN graph, analyze its properties, or perform both functions.
- 4 FINN-R: The framework converts QNNs from BinaryNet, Darknet, and Tensorpack into a common intermediate representation.Its modular frontend design allows additional framework converters to be added.
- 4 FINN-R: A quantization-aware intermediate representation tags layer inputs, parameters, and outputs with their precisions for optimization and backend mapping.The representation models the QNN as a directed acyclic graph whose nodes are layers and edges carry outputs between layers.
- 4 FINN-R: FINN-R applies transformations including direct quantization and streamlining to convert non-quantized layers and absorb scaling factors into thresholds.Direct quantization can convert parameters to specified fixed-point precision, while streamlining merges scaling into quantization.
- 4 FINN-R: Resource analysis scales hardware operators within a budget, and dataflow generation produces synthesizable FPGA implementations parameterized by determined parallelism.Backends generate deployment packages and estimates for dataflow and multilayer-offload architectures.
- 4 FINN-R: FINN-R tunes PE duplication, SIMD scaling, and multi-vector parallelization to exploit QNN concurrency and increase layer throughput.The parameters P, Q, and M are selected subject to factorization constraints that support feasible schedules.
- 4 FINN-R: Dataflow balancing progressively widens the most pressing pipeline bottleneck while resource feasibility permits, otherwise retaining multilayer offload.The algorithm begins with minimal dataflow compute and selects greater parallelism when the resource constraints remain feasible.
5 EVALUATION
FINN-R was evaluated across quantized networks, FPGA platforms, and accelerator architectures using measured implementations and comparisons with prior work. The results show strong throughput, efficiency, scalability, and prediction accuracy, alongside specific limitations for multilayer-offload estimates.
- 5.1 Experimental Setup: FINN-R evaluates four reduced-precision network topologies across embedded and datacenter FPGA platforms using dataflow and multilayer-offload architectures.The evaluation includes PYNQ-Z1, Ultra96, and AWS F1, with classifiers, multilayer perceptrons, and quantized YOLO variants.
- 5.2 Measured Results and Evaluation: The evaluated implementations were dimensioned, synthesized, and measured, with performance, power, efficiency, resource usage, and data types compared against prior work.The comparison excludes extrapolated prior results and reports only measured results where applicable.
- 5.2 Measured Results and Evaluation: Reduced precision correlates with higher achievable peak performance and energy efficiency, while CNNs attain lower peak performance than MLPs on the same platform.CNN overhead from sliding-window units and max-pooling contributes to the lower performance relative to MLPs.
- 5.2 Measured Results and Evaluation: 50 TOp/s for a fully binarized MLP and 12 TOp/s for a CNN are the best reported AWS F1 performance results.The reported values are initial results, with further gains expected from timing closure and other optimization work.
- 5.2 Measured Results and Evaluation: 433 GOp/s/W is the highest reported efficiency, achieved by FINN-R on the MLP running on Ultra96.Board-level power measurements were unavailable for the other platforms, so efficiency is reported only for embedded platforms.
- 5.2 Measured Results and Evaluation: Dataflow performance estimates are 75% - 99% accurate, whereas multilayer-offload estimates differ more because of external memory transfers and host-side feature-map reorganization.DoReFa-Net with multilayer offload on PYNQ-Z1 reached 48 % of the expected performance because host execution scales with available threads.
6 CONCLUSIONS & OUTLOOK
The paper concludes that reduced-precision FPGA inference enables broad hardware design-space exploration, and that FINN-R automates customized accelerator generation across platforms and networks. It reports measured throughput of 5 TOp/s on embedded platforms and 50 TOp/s on datacenter platforms, while noting that many design variants remain unexplored.
- 6 CONCLUSIONS & OUTLOOK: Reduced-precision representations trade a small accuracy reduction for improved performance, power efficiency, and storage footprint in FPGA-based CNN inference.FPGAs support exploring architectures that use the minimum precision needed for an application's numerical accuracy.
- 6 CONCLUSIONS & OUTLOOK: FINN-R automates exploration and generation of customized hardware accelerators with arbitrary precision, flexible architectures, target platforms, and hardware cost estimation.It is the second generation of FINN and was evaluated on four reduced-precision networks spanning CIFAR-10 classification to YOLO-based object detection.
- 6 CONCLUSIONS & OUTLOOK: 5 TOp/s on embedded platforms and 50 TOp/s on datacenter platforms demonstrate the measured throughput of the generated FINN-R design endpoints.The paper describes these results as validating the workflow and framework flexibility across a broad selection of measured cases.
- 6 CONCLUSIONS & OUTLOOK: Many precision, network, platform, and implementation variants remain unexplored because the possible design-space trade-offs are vast.Future work targets tighter performance and resource predictions, more networks, greater automation, and improved accuracy through training and quantization methods.