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SOT-MRAM 300mm integration for low power and ultrafast embedded memories
K. Garello, F. Yasin, S. Couet, L. Souriau, J. Swerts, S. Rao, S. Van Beek, W. Kim, E. Liu, S. Kundu, D. Tsvetanova, N. Jossart, K. Croes, E. Grimaldi, M. Baumgartner, D. Crotti, A. Furnémont, P. Gambardella, G. S. Kar
TL;DR
The paper addresses whether SOT-MRAM can provide nonvolatile memory suitable for cache-level integration despite STT-MRAM limitations at nanosecond and sub-nanosecond scales. It integrates top-pinned perpendicular MTJs on 300 mm wafers using CMOS-compatible processes and demonstrates sub-nanosecond switching, low energy, and high endurance.
Problem
STT-MRAM cannot operate reliably at ns and sub-ns scales because of large incubation delays, while shared read/write paths can impair read reliability and stress the MTJ.
Method
The paper develops a top-pinned W-based SOT-MTJ and integrates three-terminal devices on 300 mm wafers using CMOS-compatible processes.
Results
210 ps switching and 5x10^10-event endurance are demonstrated, with SOT switching energy as low as 350 fJ at 280 ps.
Takeaways & Limitations
The demonstrated sub-ns switching and low-power performance show that SOT-MRAM has capacity to tackle SRAM cache replacement.
Abstract
from arXiv · showhide
We demonstrate for the first time full-scale integration of top-pinned perpendicular MTJ on 300 mm wafer using CMOS-compatible processes for spin-orbit torque (SOT)-MRAM architectures. We show that 62 nm devices with a W-based SOT underlayer have very large endurance (> 5x10^10), sub-ns switching time of 210 ps, and operate with power as low as 300 pJ.