Source-linked AI summary
SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices
Sandeep Kaur Kingra, Vivek Parmar, Che-Chia Chang, Boris Hudec, Tuo-Hung Hou, Manan Suri
TL;DR
The work examines analog conductance tuning and memory/storage behavior in SLIM bilayer OxRAM devices. Identical SET and RESET pulse trains enable resistance measurements after each pulse, while successive RESET pulses increase non-volatile resistance and reduce transient current.
Problem
The analysis addresses device-to-device resistance variation in bilayer OxRAM cross-bar arrays.
Method
Identical SET and RESET pulse trains are applied, with resistance measured at VREAD = -0.4/-1.5 V after each pulse.
Results
Electrode line resistance in the cross-bar layout is partially responsible for the observed device-to-device resistance variations.
Takeaways & Limitations
Successive RESET pulses gradually increase non-volatile resistance, causing the transient current through the OxRAM device to fall during SLIM operation.
Abstract
from arXiv · showhide
Von Neumann architecture based computers isolate/physically separate computation and storage units i.e. data is shuttled between computation unit (processor) and memory unit to realize logic/ arithmetic and storage functions. This to-and-fro movement of data leads to a fundamental limitation of modern computers, known as the memory wall. Logic in-Memory (LIM) approaches aim to address this bottleneck by computing inside the memory units and thereby eliminating the energy-intensive and time-consuming data movement. However, most LIM approaches reported in literature are not truly "simultaneous" as during LIM operation the bitcell can be used only as a Memory cell or only as a Logic cell. The bitcell is not capable of storing both the Memory/Logic outputs simultaneously. Here, we propose a novel 'Simultaneous Logic in-Memory' (SLIM) methodology that allows to implement both Memory and Logic operations simultaneously on the same bitcell in a non-destructive manner without losing the previously stored Memory state. Through extensive experiments we demonstrate the SLIM methodology using non-filamentary bilayer analog OxRAM devices with NMOS transistors (2T-1R bitcell). Detailed programming scheme, array level implementation and controller architecture are also proposed. Furthermore, to study the impact of introducing SLIM array in the memory hierarchy, a simple image processing application (edge detection) is also investigated. It has been estimated that by performing all computations inside the SLIM array, the total Energy Delay Product (EDP) reduces by ~ 40x in comparison to a modern-day computer. EDP saving owing to reduction in data transfer between CPU Memory is observed to be ~ 780x.
Figures:
The figures document SLIM’s bitcell, state programming, array control, and performance evaluation against conventional CPU–DRAM computing. They cover device characterization, logic and memory operation, and application-level comparison.
- Architecture and device: SLIM combines storage and logic operations simultaneously and non-destructively in memory blocks using a 2T-1R bitcell and bilayer OxRAM device.The figures also show the proposed processing architecture and the fabricated Ni/HfO2/ATO/TiN device.
- State programming: Four resistance states—‘11’, ‘10’, ‘01’, and ‘00’—support distinct Logic and Memory assignments, with programming signals defining Memory–Logic transitions.The states are evaluated through resistance distributions, endurance over 200 cycles, and example Memory Write operations.
- Logic operation: NOR logic is experimentally implemented for four operand combinations, while intelligent read and refresh are included in the SLIM operation flowcharts.The same figure presents both Memory Write and Logic operation procedures.
- Performance and application: 64-bit Logic operations are compared between the SLIM array and a CPU fetching operands from DDR3 DRAM, alongside edge-detection outputs for CPU–DRAM and CPU–SLIM systems.The comparison is framed around performance and energy, while the application figure shows outputs with the original image.
- Performance metrics: Table 3 organizes SLIM bitcell count, normalized Energy/Operation, and normalized Latency count for operations implemented with the SLIM NOR gate.These quantities are reported as operation-level measures for different logic functions.
- Comparative evaluation: Table 4 reports edge-detection performance for conventional and SLIM-based system configurations, while Table 5 compares OxRAM-based LIM methodologies with SLIM.The tables provide application-level and literature-comparison views of the proposed approach.
S3. Transistor Characteristics
The supplementary material documents the measurement setup and electrical characterization used to evaluate SLIM transistor and memory operations. It includes instrumented OxRAM signals, programming outcomes, and transient-current behavior.
- Transistor characteristics: NMOS characterization includes ID–VDS and ID–VGS plots plus the relationship between enforced compliance current, ON resistance, and gate voltage.The measurements use VDS = 3 V for the compliance-current and ON-resistance relationship.
- Measurement setup: SLIM characterization uses integrated 2T-1R bitcells, CMOS and OxRAM chips, and a parameter analyzer.The setup is identified as the experimental platform for SLIM measurements.
- Memory operation: Memory Write ‘1’ and ‘0’ operations are measured from multiple initial resistance states using transient OxRAM current and applied programming signals.The experiments cover transitions to the absolute Memory states ‘11’ and ‘01’.
- Measured response: During successive reset pulses, transient OxRAM current falls as the non-volatile resistance gradually increases.The reported signal behavior explains the current trend in the Memory/Storage measurements.
S6. Circuit schematics for different operand combination for realizing NOR Operation using 2T-1R bitcell
The circuit schematics enumerate all four two-input operand combinations for realizing NOR with the 2T-1R SLIM bitcell and map each case to its applied signals.
- Operand combinations: The four operand cases are a=b=‘0’, a=‘0’, b=‘1’, a=‘1’, b=‘0’, and a=b=‘1’.Each case corresponds to one row of the NOR truth table and its proposed signal mapping.
- Signal mapping: The signal conditions use VTB = VTE – VBE, VG = 10 V for 7 ms, and V2 = P3 = 5.5 V for 7 ms.These values specify the illustrated NOR-operation control signals.
S7. Principle of Refresh mechanism
The refresh mechanism coordinates multiple 8x8 SLIM mats by tracking row-level Logic use and triggering refresh when the tracked rows are exhausted. Device parameters for the SLIM array are listed separately.
- Tag tracking: Each 8x8 SLIM mat receives one Tag byte, with one tag bit per row tracking whether that row was used for Logic.The Tag byte is initialized to zero when a fresh mat is used.
- Refresh trigger: When all Tag-byte bits become ‘1’, the Refresh block is triggered for the SLIM mat.This implements the optimized refresh policy across multiple mats.
- System context: The memory-hierarchy figure contrasts conventional DRAM-based organization with a SLIM array capable of both Storage and Logic operations.It also relates SLIM to neuromorphic computing and identifies device parameters for the array.