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Low-Power Neuromorphic Hardware for Signal Processing Applications

Bipin Rajendran, Abu Sebastian, Michael Schmuker, Narayan Srinivasa, Evangelos Eleftheriou

arXiv:1901.03690v3cs.ETcs.LGcs.NE

TL;DR

High-energy conventional machine-learning systems motivate brain-inspired spiking and neuromorphic approaches. The paper reviews architectures and system-level design choices that emulate time-based neural processing and mitigate the von Neumann bottleneck, alongside reported hardware and application results.

  • Problem

    The von Neumann bottleneck limits performance through the separation of computation and data storage, complicating efficient implementation of spiking neural networks.

  • Method

    The paper reviews design objectives and approaches for energy-efficient neuromorphic platforms that emulate time-based spiking computation.

  • Results

    84.5% accuracy and 15 nJ per inference were reported for on-chip learning on the ODIN chip.

  • Takeaways & Limitations

    Neuromorphic systems use collocated memory and processing to address the von Neumann bottleneck while supporting event-based neural computation.

Abstract

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Machine learning has emerged as the dominant tool for implementing complex cognitive tasks that require supervised, unsupervised, and reinforcement learning. While the resulting machines have demonstrated in some cases even super-human performance, their energy consumption has often proved to be prohibitive in the absence of costly super-computers. Most state-of-the-art machine learning solutions are based on memory-less models of neurons. This is unlike the neurons in the human brain, which encode and process information using temporal information in spike events. The different computing principles underlying biological neurons and how they combine together to efficiently process information is believed to be a key factor behind their superior efficiency compared to current machine learning systems. Inspired by the time-encoding mechanism used by the brain, third generation spiking neural networks (SNNs) are being studied for building a new class of information processing engines. Modern computing systems based on the von Neumann architecture, however, are ill-suited for efficiently implementing SNNs, since their performance is limited by the need to constantly shuttle data between physically separated logic and memory units. Hence, novel computational architectures that address the von Neumann bottleneck are necessary in order to build systems that can implement SNNs with low energy budgets. In this paper, we review some of the architectural and system level design aspects involved in developing a new class of brain-inspired information processing engines that mimic the time-based information encoding and processing aspects of the brain.

I. INTRODUCTION

Conventional computing faces a bottleneck between computation and storage, while brain-inspired spiking systems encode information in timed events. Neuromorphic platforms address this gap by colocating memory and computation, distributing simple units, and communicating through spikes.

  • The von Neumann bottleneck is a performance limitation caused by the chokepoint between computation and data storage.
  • Spiking neural networks use time-based information encoding and processing inspired by the brain.
  • Neuromorphic platforms distribute computation and memory across simple neuron-like units that communicate through asynchronous spikes and synapses.
  • Collocated memory and processing, increased parallelism, and reduced energy budgets have been demonstrated in neuromorphic implementations.
  • The paper reviews design objectives and approaches for building energy-efficient neuromorphic computing platforms.
  • Brain computing uses timed spikes as messages, with neurons integrating synaptic changes over time before emitting spikes under suitable conditions.

A. Signal encoding in the brain

Brain-inspired signal processing encodes changes as sparse, event-driven spikes rather than uniformly sampled values. This timing-based representation supports reactive processing and motivates algorithms designed specifically for event-based sensing and inference.

  • Event-driven sensory encoding produces spikes when stimulus changes cross thresholds, rather than continuously transmitting uniformly sampled values.
  • The encoding produces a sparse code that transmits information only when the input signal changes.
  • Unlike fixed-rate sampling, event-driven encoding is not limited by a fixed sample rate in the maximum frequency it can encode.
  • Feature-extraction latency can depend on the minimum delay between events rather than the interval between samples, enabling highly reactive systems.
  • Spike-timing-dependent plasticity strengthens or weakens synapses according to the temporal order of pre- and postsynaptic spikes.
  • The brain’s massively parallel, event-driven computing and connectivity are presented as likely contributors to efficient signal processing, inference, and control.

III. BUILDING BLOCKS OF NEUROMORPHIC SYSTEMS

Neuromorphic hardware models essential neuronal and synaptic dynamics with simplified circuits. Its central implementation challenge is supporting arbitrary, high-fan-out yet sparse connectivity while balancing hardware trade-offs.

  • Hardware implementations commonly use simplified neuron models because they are easier to implement and scale than biologically detailed dynamics.
  • The leaky integrate-and-fire model integrates synaptic current until membrane voltage crosses a threshold, then emits a spike and resets.
  • Most hardware synapses simplify biological transmission by using current models that are independent of the postsynaptic neuron’s potential.
  • Synaptic current is modeled as a weighted sum of spike-triggered kernels, with kernel choice determining the temporal current response.
  • Hardware designs trade off area, power, reliability, and performance when implementing neuronal and synaptic circuits.
  • The major system challenge is supporting arbitrary connectivity patterns while preserving high fan-out and sparse neural connections.

IV. SYSTEM DESIGN PRINCIPLES AND APPROACHES

Neuromorphic architectures mitigate the von Neumann bottleneck by placing memory and computation within neurosynaptic cores. Local crossbars provide dense connectivity, while asynchronous AER networks support sparse long-range communication across cores.

  • Collocating memory and computation within neurosynaptic cores mitigates the von Neumann bottleneck.
  • A neuromorphic accelerator typically comprises interconnected neurosynaptic cores that integrate neurons and synapses locally.
  • Each core commonly uses a crossbar array with electronic synapses at cross-points and peripheral circuitry for routing, storage, and neuronal functions.
  • AER enables flexible off-chip interconnects and asynchronous communication between cores in large-scale multi-chip platforms.
  • Address-event representation assigns each neuron an address and transmits that address when the neuron spikes, implicitly encoding spike time.
  • Crossbar arrays model dense local connectivity, whereas AER network topologies support sparse long-range connections.

V. STATE-OF-THE-ART NEUROMORPHIC HARDWARE

State-of-the-art neuromorphic platforms implement large-scale spiking networks using event-driven communication, distributed processing, and memory colocated with computation. SpiNNaker and TrueNorth demonstrate scalable digital architectures with different trade-offs in programmability, connectivity, and energy efficiency.

  • SpiNNaker: SpiNNaker uses processor cores and event-driven packet handling to simulate large spiking networks with distributed local memory and no global memory.Messages arriving at a core trigger interrupts, and the system routes small packets through a high-throughput fabric.
  • SpiNNaker: SpiNNaker scales from multi-core chips and boards to a system containing 1 million processors housed in ten racks.Its boards connect 48 chips, with up to 864 cores per board depending on manufacturing yield.
  • SpiNNaker: PyNN provides a portable interface for implementing spiking networks across simulators and hardware, including standard neuron models and STDP.SpiNNaker 2 adds more cores and linear algebra accelerators and has been used for deep learning with sparse connectivity.
  • TrueNorth: TrueNorth integrates 4096 neurosynaptic cores, each with local SRAM storing synapse states, neuron states, parameters, addresses, and axonal delays.Its digital neurons implement leaky-integrate-and-fire dynamics and time-multiplex up to 256 neurons per core.
  • TrueNorth: 46 billion synaptic operations per second and 26 picojoules per synaptic event characterize TrueNorth’s real-time operation.The chip combines event-driven custom design, colocated memory and processing, and low-leakage CMOS technology.
  • TrueNorth: TrueNorth’s 20 mW/cm2 power density is about 3 orders of magnitude smaller than that of typical CPUs.Its spike-based communication supports programmable fan-in and fan-out up to 256 per core.

C. Loihi

Loihi is a programmable neuromorphic learning chip designed to scale spiking connectivity and support diverse learning rules. It delivers substantial synaptic throughput at low energy while providing software access through the Nengo simulator.

  • Implementation: Loihi integrates 128 neural cores with 1024 spiking neurons and 2 Mb SRAM per core, plus three embedded x86 processors and 16 MB of synaptic SRAM.The chip supports synaptic bit resolutions from 1 to 9 bits and approximately 130,000 neurons and 130 million synapses.
  • Architecture: Loihi supports up to 4096 on-chip cores and 16,384 chips through hierarchical addressing, targeting biological-scale fan-out of 1000.Core-to-core multicast and population-based hierarchical connectivity address network-scaling requirements.
  • Learning: Loihi cores use microcodes to implement pairwise STDP, triplet STDP, reinforcement learning protocols, and spike-rate or spike-timing rules.The chip also supports axonal and synaptic delays, threshold adaptation, and reward-modulated learning.
  • Performance: 30 billion synaptic operations per second at about 15 picojoules per synaptic operation characterize Loihi at nominal operating conditions.A Python package for Nengo enables studying spiking-network implementations without direct hardware access.
  • BrainScaleS: BrainScaleS combines analog neuron circuits with digital communication and supports accelerated spiking-network emulation.Its speedup factor of 10^3 to 10^4 allows 1 second of wall time to emulate up to 10,000 seconds of biological simulation.

E. NeuroGrid/Braindrop

NeuroGrid and related neuromorphic platforms combine mixed-signal neural computation with scalable routing and programmable connectivity. Implementations span large neural models, configurable neuron dynamics, and on-chip learning.

  • NeuroGrid uses analog/digital mixed-signal subthreshold circuits to emulate continuous-time neuronal and synaptic functions.Its transistor physics directly emulates neuronal and synaptic behavior.
  • The platform combines 16 NeuroCore chips, each containing a 256×256 array of two-compartment neurons and asynchronous multicast routing.
  • NeuroGrid can implement cortical models with up to one million neurons and billions of synaptic connections.
  • DYNAP-family designs combine hierarchical asynchronous routing with analog variability for configurable networks, neural sampling, and reservoir computing.
  • DYNAP-SE integrates 1024 neurons and 64k synapses, using subthreshold analog circuits for temporal dynamics and digital circuits for runtime connectivity programming.
  • ODIN: On a subset of pre-processed MNIST images, on-chip learning achieved 84.5% accuracy while consuming 15 nJ per inference.

VI. NEUROMORPHIC COMPUTING WITH MEMRISTIVE DEVICES

Memristive devices provide programmable resistance states and accumulation mechanisms that can emulate neuronal dynamics and synaptic behavior. Their neuromorphic use offers efficiency potential but remains constrained by device variability, dynamic range, and circuit overhead.

  • Memristive devices support multiple resistance states and incremental conductance changes under successive programming pulses.These properties underpin their use for neuromorphic computation.
  • Neuronal dynamics: PCM devices can represent a neuron’s internal state through phase configuration and tune firing frequency proportionally to input strength.
  • Neuronal dynamics: PCM-based neurons exhibit inter- and intra-neuronal randomness, enabling stochastic neuronal behavior and population-based computation.
  • Neuronal dynamics: Population coding accurately represents fast signals even when individual phase-change neurons have slow firing rates.The cited example uses 500 slow-firing stochastic phase-change neurons.
  • Synaptic communication: Crossbar architectures implement synaptic efficacy through device current and synaptic plasticity through parallel conductance updates.Read voltages measure synaptic output, while write pulses change synaptic weights.
  • Challenges: Despite these challenges, nanoscale memristive devices are expected to improve areal and power efficiency in neuromorphic processors.

VII. SIGNAL PROCESSING APPLICATIONS

Neuromorphic platforms support signal-processing applications through sparse, event-driven computation, local learning, and specialized hardware. Demonstrations span classification, gesture detection, optimization, brain-machine interfaces, and unsupervised correlation detection.

  • Neuromorphic computation: Fewer than 2000 spikes learned image features conventionally represented using more than 100,000 pixels.The example uses balanced excitatory and inhibitory spiking activity for efficient learning.
  • Neuromorphic computation: Asynchronous SNN processors exploit sparse spike events and local learning to reduce memory requirements and training time compared with traditional machine-learning systems.Processing occurs only during spike events, while sparse connectivity minimizes stored parameters and training time.
  • Application demonstrations: TrueNorth achieved software-equivalent performance on several benchmark pattern-classification tasks using low-precision synaptic weights.A modified backpropagation rule made the trained weights and neuronal dynamics portable to the hardware.
  • Application demonstrations: Intel Loihi delivered over three orders of magnitude improvement in energy-delay product over CPU solvers for LASSO optimization.The implementation used a spiking convolutional form of the Locally Competitive Algorithm.
  • Application demonstrations: PCM-synapse SNNs separated correlated and uncorrelated inputs despite significant device-to-device variability and conductance drift.In the experiment, 144,000 streams were applied through more than one million PCM devices, producing well-separated final synaptic distributions.

VIII. FUTURE OUTLOOK

Future progress in low-power brain-inspired computing is expected to proceed from CMOS neuromorphic accelerators toward larger platforms using nanoscale memristive computational memories. The field still faces unresolved algorithmic, device, and scaling challenges.

  • Algorithmic challenges: SNNs have not conclusively demonstrated superior performance to conventional deep learning in accuracy and, in many cases, energy efficiency.The paper attributes the gap to limitations in supervised learning, local learning rules, and reliance on rate coding.
  • Algorithmic challenges: Recent approaches use temporal coding, adaptive recurrent neurons, network conversion, and spiking units trained with backpropagation through time.These approaches include classification comparable to state-of-the-art LSTM networks and conversions with negligible accuracy loss.
  • Technology challenges: Memristive neuromorphic systems face conductance variation over time and temperature, along with nonlinear and stochastic accumulation that creates scaling challenges.Multi-cell architectures are identified as a promising response to these issues.
  • Technology outlook: Near-term innovation is expected from neuromorphic accelerators built with conventional low-power mixed-signal CMOS architectures.The paper describes these accelerators as the first stage of future field innovation.
  • Technology outlook: A later stage is expected to use ultra-low-power computational memories based on nanoscale memristive technologies.The outlook links these technologies to large neuromorphic platforms.
  • Technology outlook: Algorithmic exploration must proceed together with hardware advances for applications constrained by power and area, including mobile devices, robotics, IoT, and personalized medicine.The paper also points to opportunities from new materials and device structures beyond standard CMOS as CMOS scaling slows.

IX. AUTHORS AND BIOS

The paper’s authors are researchers and inventors working across brain-inspired computing, neuromorphic algorithms, in-memory computing, sensory processing, and neuromorphic hardware.

  • Author biographies: Abu Sebastian leads IBM Research Zurich’s in-memory-computing effort after contributing to storage and memory technology projects.His biography identifies him as a Principal Research Staff Member and Master Inventor.
  • Author biographies: Michael Schmuker is a data-science researcher translating neurobiological sensory-computing principles into algorithms, with a focus on neuromorphic olfaction and gas-based navigation.His background spans biology, chemistry, computational neuroscience, and neuromorphic computing.
  • Author biographies: Narayan Srinivasa leads machine-intelligence research at Intel Labs and has worked on ultra-low-power AI and the Loihi neuromorphic chip.His prior work includes leadership in neural and emergent systems and the DARPA SyNAPSE, Physical Intelligence, and UPSIDE programs.
  • Author biographies: Evangelos S. Eleftheriou is an IBM Fellow associated with neuromorphic computing, communications, and multiple IEEE and technology awards.His biography identifies roles at IBM Research Zurich and IBM’s T. J. Watson Research Center.
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